Tang Sau Keat
Penang
Summary
Current Position : SoC Design Engineer.
Current Company : Intel Corporation (M) Sdn. Bhd. Current Specialization : SoC/ASIC/VLSI Physical design. Highest Education : Bachelor's Degree in Electrical & Electronic Engineering Years of Experiences : 27 years
Overview
27
27
years of professional experience
Work History
SoC Design Engineer
Intel Corporation
11.2016 - 07.2023
- Engaged in physical verification of module/subsystem.
- Collaborated in fullchip SoC integration to ensure compliance with the design rules.
- Collaborated with team members for the successful completion of SoC physical verification. Provided valuable insights to module owner on required fixes.
- Engaged in mock tape-out exercises to optimize and streamline the tape-out process
- Contributed to the successful completion of fullchip GDS tape-out and submission of the final GDS to the foundry.
- Collaborated with other team members to ensure successful design, synthesis, and verification of complex SoC.
Mask Design Engineer, Member of Technical Staff
Altera Corporation (M) Sdn. Bhd.
06.1996 - 11.2016
- Handled various process node projects from 0.25um to 14nm for the last 20 years of experience.
- Collaborated on the planning and execution of Altera CPLD and FPGA product physical design projects.
- Responsible for full chip integration and milestone coordination, and ensuring a smooth tapeout.
- Involvement in planning and executing physical layout for various IP and Product teams
- Familiarised with layout custom design incorporating analog requirement.
- Involved in the LVDS Clock Tree detail planning and layout execution.
- Participated in DPA/Serdes planning and executed physical layout
- Led multiple projects as a block, co-lead, and project leader position.
- Planned and aligned schedules with internal layout and ICD to deliver database components. Utilised project management skills for resource planning, block size estimation, aligning tools and flows with the Design Automation team. Conducted regular meetings to provide status updates, resolve critical issues, and ensure project closure.
- Collaborated on diverse methodologies to enhance project productivity and efficiency.
- Collaborated with designer in multiple iterations to enhance the performance of IR drop database for better PDN
Education
Bachelor's Degree - Electrical / Electronic
Lincoln University
01.2003
HND for B.Eng - Electrical and Electronic Engineering
PSDC
Malaysia01.1996
Lower/Upper Sixth - Science Stream
Ching Ling High School
01.1993
Secondary School -
Ching Ling High School
01.1991
Skills
- Project Management Skills
- Backend EDA tools including Cadence and Calibre
- Submicron (7nm) design process environment
- Physical verification including DRC/LVS/ERC
- Microsoft Office/Project
- Unix/Linux environment
- Perl/Tcl/shell scripting
- VLSI design flow
- IP custom layout
- Block level floorplanning
- Fullchip level integration and verifications
- Fullchip mock tape-out preparation
Transport
Yes (in Malaysia)
Personal Information
- Available: Immediately (preferable 1st October 2024)
- IC Number: 731209-07-5273
- Date of Birth: 12/09/73
- Gender: Male
- Nationality: Malaysia
Languages
- English, 8, 7
- Bahasa Malaysia, 7, 7
- Mandarin, 8, 7
References
Law Liang Ming, +6016-4408833, liang.ming.law@intel.com, Soc Design Manager, Intel Corporation (M) Sdn. Bhd.
James Lim Chee Hong, James.chee.hong.lim@intel.com, Soc Design Director, Intel Corporation (M) Sdn. Bhd.
Timeline
SoC Design Engineer
Intel Corporation
11.2016 - 07.2023
Mask Design Engineer, Member of Technical Staff
Altera Corporation (M) Sdn. Bhd.
06.1996 - 11.2016
Bachelor's Degree - Electrical / Electronic
Lincoln University
HND for B.Eng - Electrical and Electronic Engineering
PSDC
Lower/Upper Sixth - Science Stream
Ching Ling High School
Secondary School -
Ching Ling High School
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