Rajat Mishra
SOC Logic Design Engineer
Bengaluru
Summary
Organized and dependable candidate successful at managing multiple priorities with a positive attitude. Willingness to take on added responsibilities to meet team goals.
Overview
1
1
year of professional experience
6
6
years of post-secondary education
Work History
SoC Design Engineer
Intel
06.2023 - Current
- Mentored junior engineers on best practices in SoC design engineering, fostering a culture of continuous improvement and technical excellence.
- Presented project updates to senior management teams during periodic review meetings, demonstrating progress and addressing any concerns.
- Championed the adoption of low-power design techniques across the team, resulting in significant energy efficiency improvements in final products.
- Performed detailed analysis of design trade-offs, making informed decisions that balanced power, performance, and area constraints.
- Contributed to the development of internal design guidelines and best practices documentation, raising the overall quality bar for future projects.
- Delivered high-quality RTL code for complex blocks within aggressive project schedules, meeting or exceeding all performance targets.
- Enhanced design efficiency by implementing advanced synthesis methodologies and utilizing industry-standard EDA tools.
- Optimized SoC designs by implementing power reduction techniques and clock gating strategies.
- Completed calculations and design simulations to assess power needs and choose optimal components.
Education
Master of Technology in VLSI -
National Institute of Technology, Delhi
08.2021 - 05.2023
Bachelor of Technology in Electronics & Communication Engineering - undefined
KIET Group of Institutions, Ghaziabad
07.2016 - 05.2020
Higher Secondary School -
Lucknow Public School
02.2015 -
Secondary School -
Lucknow Public School
03.2013 -
Skills
HDL: Verilog
CDC Clock Domain Crossing
VCLP
UPF
Digital Design
TFM (Tool Flow methodology using Script)
Gate Level Simulation
Verdi Tool
IP Integration
Low Power Design
Projects
- EBB (Embedded building blocks) Integration in SOC, INTEL Internship
- Display IP Integration into SOC, Intel as a Full Time Employee
- Power and Performance optimization in IP, Intel as a Full Time Employee
- Gate Level Simulation into SOC, Intel as a Full Time Employee
- Tool Flow methodology using Script, Intel as a Full Time Employee / Intern
- Technique to Reduce Power Consumption in two-stage CMOS technology Comparator, B. Tech (Final Year)
Research Paper Publications
- A Modified Dynamic Comparator for Lowering Peak Kink in Differential Amplifier and Latch, ICAPSM 2022, B. Tech, First and Second Year
- High-Speed Vacuum Air Vehicle, International Maglev board, First author, St. Petersburg, Russia
- High-speed Magnetic Levitating Transportation using compressed air, 978-613-8-83718-3, scholar's press, Germany
- System to minimize fuel energy in propulsion, IEEE Aerospace Conference, Letter of acceptance, Montana, USA
Achievements/Participations
- GATE qualified (2020/2021)
- Participated in NCSE (National children science congress) twice at the school level
- Participated in 'Swachh Bharat Abhiyan held by swachhta pakhwada in 2018
- Participated in badminton tournaments in college
- Organized college event INNOTECH 2017 and EPOQUE@PRASTUTI 2018
- Participated in a chess tournament in college
- Our team's idea got selected in "Techkriti" held by IIT Kanpur at the school level
Attributes
Consistent performer, Initiative to work independently, Good Management and Leadership skills, easily adaptable to any environment, Travelling, Listening to Music, Badminton, Cycling
Timeline
SoC Design Engineer
Intel
06.2023 - Current
Master of Technology in VLSI -
National Institute of Technology, Delhi
08.2021 - 05.2023
Bachelor of Technology in Electronics & Communication Engineering - undefined
KIET Group of Institutions, Ghaziabad
07.2016 - 05.2020
Higher Secondary School -
Lucknow Public School
02.2015 -
Secondary School -
Lucknow Public School
03.2013 -