Mohamad Farid Buni
IP Design Verification Engineer
Cyberjaya
Summary
Experienced IP Design Validation Engineer with over 4 years at Intel, specializing in RTL verification using SystemVerilog and UVM. Skilled in developing robust testbenches, writing reusable verification components, and debugging pre-silicon issues across multiple IP domains including Type C, Display, USB, and Power Management. Passionate about functional coverage, simulation efficiency, and delivering first-silicon success through disciplined and methodical verification practices.
Overview
5
5
years of professional experience
6
6
years of post-secondary education
Work History
IP Design Validation Engineer
Intel Corporation
Bayan Lepas, Penang, Penang
01.2020 - Current
- Spearhead functional verification of IP logic, ensuring adherence to specification requirements and microarchitecture specifications.
- Develop comprehensive IP verification plans, test benches, and verification environments to ensure coverage and compliance.
- Execute verification plans, utilizing advanced tools such as Cadence Maestro, Cadence Perspec, Logic Analyzer, Oscilloscope, Windows debugger, and KDB.
- Employ diverse debugging methods including hardware register checking, SystemVerilog RTL tracing, and software/driver code tracing for efficient resolution of complex issues.
- Take charge of replicating, root causing, and debugging issues in the pre-silicon environment, implementing corrective measures for failing tests.
- Document test plans and drive technical reviews with design and architecture teams.
- Build and develop validation test plans and test scenarios, collaborating extensively with cross-functional teams to ensure comprehensive test coverage.
- Areas of expertise encompass Type C Subsystem, Display Engine, USB, and Power Management Engine.
- Programming Skills: Proficient in SystemVerilog, Verilog, C++, Python, Bash, Linux, and C#. Skilled in digital design verification, test automation, and developing test content using Cadence Maestro/Perspec tools.
- Advanced Debugging Techniques: Experienced in employing diverse debugging methods, including hardware register checking, SystemVerilog RTL tracing, and software/driver code tracing for efficient resolution of complex issues.
- Cross-Functional Collaboration: Strong ability to collaborate closely with architects, RTL developers, and physical design teams to enhance verification of complex features.
- Continuous Integration Tools: Experienced in using CI tools like GitHub, Git, and Jenkins for version control, continuous integration, and automation of testing and deployment processes.
- Mentored junior engineers in best practices for validation engineering methodologies improving team skillsets.
Education
MENG (HONS) - ELECTRICAL ENGINEERING
The University of Sheffield
Sheffield, UK 08.2016 - 07.2020
MALAYSIAN CERTIFICATE OF EDUCATION -
SM Sains Muar
Johor 01.2012 - 12.2013
Skills
- UVM/SystemVerilog/RTL Tracing
C/C#
Python
Effective communication
Attention to detail
Time management
Timeline
IP Design Validation Engineer
Intel Corporation
01.2020 - Current
MENG (HONS) - ELECTRICAL ENGINEERING
The University of Sheffield
08.2016 - 07.2020
MALAYSIAN CERTIFICATE OF EDUCATION -
SM Sains Muar
01.2012 - 12.2013
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