Abdul Hafiz Mustafa

• Managed CIP Project layer for thick gates standard cell based for Samsung S8 and Intel I3 processes, overseeing configuration, maintenance, and defining common recipes.
• Successfully made multiple official project layer releases, notifying Logic Team and external teams.
• Resolved issues in IP BE flows, including Fusion Compiler runs (up to synthesis), FEV, SAGE ATPG, and Caliber verification flow.
• Executed BE TFM through Cheetah environment for Storage and Power Domain IPs, successfully delivering IPs for several milestones.

• Ran simulations primarily using PrimePower to analyze power component data, gate count, and area for partition-level PCH SoC across ongoing SD milestones in various projects.
• Analyzed data to identify power and area trends based on official releases from SD, enabling Power Modeling owners to establish KPIs using Vectored simulation runs.
• Conducted weekly PrimePower Work Group meetings to manage simulation run requests and drive enhancements to the standalone script maintained by Power Modeling PrimePower team.
• Implemented PrimePower workgroup MS OneNote to significantly enhance Work Group interactions, collaborations, and accessibility, leading to improved communication and seamless access across the PrimePower team and other functions.

• Physical structure implementation for Embedded Memory Test Chips and Logic Test Chips with different process nodes.
• Experienced in block level and fullchip level implementation.
• Fullchip support which includes debugging and suggesting solutions for PNR, PV, STA and documentation.
• Setup design flows before/early stage of project such as for PV and PNR flows.
• Maintenance of design flows throughout project to converge on stable/quality design.
• Involved in development and maintenance of Centralize Flow under Physical Verification for LVS, ANT and other process specific flows.
• Appointed as one of 'champion' for PV and STA under Malaysia team where different design sites can refer to.
• Assigned to misc. task such as creating perl script to convert csv to core RTL for Logic Test Chip.
• Experienced process nodes: 7nm, 12nm,14nm , 22nm, 55nm

Worked on structural implementation and synthesis:

• DCH block - 1.2GHz, 2 mil gates, Synthesis, PNR and STA.
• SYS subsystem - 650MHz, 6 mil gates, soft-macro IP, Synthesis and STA.
• AI block - 650MHz, 4.6 mil gates, PNR and STA.
• FCLDPC subsystem - 1.2GHz, PNR.
• Involved in two rev cycles of a product (prototype) for 16nm process node.
• Feedback issues with the PNR flow and suggesting solutions/findings.
• Mentor juniors in PNR area.

Involved in Physical Verification projects for 10nm and 14nm process nodes.

• Fixed block level DRC, LVS and DFM requirements.
• Created tcl scripts to ease DRC fixing experience for the team.