Summary
Overview
Work History
Education
Skills
Timeline
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Vincent Sia Ing Teck

Vincent Sia Ing Teck

Pre-Silicon Validation Engineer
Bayan Lepas, Penang

Summary

Qualified IP system validation engineer with background in PCIe/CXL design verification. Proven track record in developing and implementing verification strategies that enhance product reliability. Demonstrated ability to troubleshoot, debug complex systems' issues and collaborate effectively with cross-functional teams for swift resolution to ensure high quality IP system design.

Overview

7
7
years of professional experience

Work History

IP Design Verification Engineer

Intel Microelectronics (M) Sdn Bhd
04.2022 - Current
  • Involved in detailed validation of PCIe, CXL designs on system-level emulation, particularly on logical-physical layer features (PM states, LTSSM, etc.).
  • Developed comprehensive test plans based on requirements analysis, ensuring thorough coverage of all critical aspects of design functionality and corner cases.
  • Effective and targeted debugging of RTL logic issues, consistent bug tracking, and communication with design teams to ensure fast resolution and quality design.

Engineering Intern

Intel Microelectronics (M) Sdn Bhd
07.2021 - 09.2021
  • Completed the MoHE Elite Internship Programme.
  • Gained hands-on experience in various engineering tools, software, and techniques to contribute effectively to multiple projects.

Electrical Drafter

Miri Powerline Electrical Engineering Sdn Bhd
07.2018 - 09.2018
  • Interpreted project specifications and delivered layouts for new electrical systems, particularly main switchboard drafts for industrial buildings and marine vessels.
  • On-hand technical training, testing, and commissioning of main switchboards before shipping out to customers.

Education

Bachelor of Electronic Engineering With Honours -

University Tun Hussein Onn Malaysia
Johor
04.2001 -

Diploma in Electrical Engineering -

University Tun Hussein Onn Malaysia
Johor
04.2001 -

Skills

Fast technical learning, problem solver, effective communicator

IP System verification (test plan, debug), Verilog RTL code interpretation & analysis

Timeline

IP Design Verification Engineer

Intel Microelectronics (M) Sdn Bhd
04.2022 - Current

Engineering Intern

Intel Microelectronics (M) Sdn Bhd
07.2021 - 09.2021

Electrical Drafter

Miri Powerline Electrical Engineering Sdn Bhd
07.2018 - 09.2018

Bachelor of Electronic Engineering With Honours -

University Tun Hussein Onn Malaysia
04.2001 -

Diploma in Electrical Engineering -

University Tun Hussein Onn Malaysia
04.2001 -

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Vincent Sia Ing Teck Pre-Silicon Validation Engineer