TRILOK THIMMA REDDY JANAKALOTI
Bayan Lepas, Penang, Malaysia,07
Summary
Experienced Design Engineer with over 8 years in the semiconductor industry, specializing in FPGA design, Embedded Programming and Post Silicon Validation. Proficient in RTL coding, design debugging, and FPGA implementation using AMD/Xilinix Vivado, and Intel/Altera Quartus. Skilled in industry-standard protocols (AHB, AXI, I2C, SPI, Ethernet, UART etc) and knowledgeable in ARM/RISC-V architectures. Excellent communication and collaboration skills, with a proven track record of delivering high-quality prototypes and supporting cross- functional teams.
Overview
9
9
years of professional experience
Work History
FPGA Silicon Validation Engineer
Intel Microelectronics (M) Sdn. Bhd
01.2022 - Current
- Led the Fabric Network on Chip (NoC) Debug for Design for Debug (DFD) Validation.
- Developed and verified RTL in a Design Verification (DV) environment.
- Created Validation Soft IP (VSIP) and implemented FPGA design.
- Automated Quartus design creation and optimization.
- Developed comprehensive test cases using Tcl for thorough validation.
- Identified and resolved 3 critical bugs in Quartus device modeling and assembler.
- Collaborated with cross-functional teams to enhance design and debugging processes.
- Provided ongoing support and maintenance for prototype designs.
- Ensured critical path timing closure and conducted extensive RTL simulation.
Validation Engineer II
DSS Software Solutions Sdn Bhd
08.2020 - 12.2021
- Defining micro-architecture and implementing RTL for AXI based soft IPs in Verilog to Validate the Agilex FPGA bridges
- Written Self checking Test bench to perform functional verification of AXI based soft IPs using BFMs in Modelsim
- Integrated AXI soft IPs with Intel Agilex Hard Processor Sytem(HPS)
- Developed Bare metal code(test cases) using C language for HPS
- Executed Bare metal code in U-boot, DS-5 and performed functional test
- Developed Tcl script to verify functionality of the FPGA region using System Console
- In HPS regression, wrote Python script to automate the .sof file generation, remove certain lines in .qsf file and archive project
- Developed scalable Quartus Project using NIOS cores
- The design size(LE's) can be increased/decreased by simply changing few parameters inside Tcl script.
FPGA Design Engineer
Benchmark Electronics
04.2019 - 08.2020
- Implemented FPGA designs (VHDL) including RTL coding, Soft CPU NIOS II generating, and IP integration, ensuring compliance with design specifications.
- Led board bring-up activities and tested overall system functionality, demonstrating strong problem-solving skills and attention to detail.
- Developed low and high-level device drivers for Soft CPU NIOS II using C language, facilitating efficient communication between FPGA components and peripherals.
- Designed and implemented DSP Control System Algorithms targeted for Intel Cyclone 10 using ADC & DAC, contributing to the development of advanced control systems.
Senior Engineer
Sigma Microsystems Pvt Ltd
01.2016 - 04.2019
- Design, development and debug of RTL in simulations and FPGA systems
- Interfacing RTL logic with Embedded Hardcore/Soft-core processors like on- chip ARM Processor/ FPGA based Microblaze & NIOS, HDL IP and external peripherals
- Wrote U-Boot scripting for reconfiguring Flash and loading dual images on Xilinx Zynq SoC
- Device Driver Development for SoC based FPGAs, Microcontrollers and Microprocessors
- Ported RTOS like Linux and VxWorks on Zynq ARM Processor
- Wrote closed control loop algorithm to control Actuators in DSP using C and assembly language
- Board bring up, Software development for diagnostics and application development and Integration
- Discussed project progress with customers, collected feedback on different stages and directly addressed concerns.
Education
Bachelor of Engineering - Electronics And Communications Engineering
VTU - Visvesvaraya Technological University
Karnataka, India01.2015
Skills
- IP-Based Designs: Expert in soft and hard IP-based designs, with a thorough understanding of soft and hard processors and integrating them with fabric logic
- RTL Coding: Extensive experience in RTL coding using Verilog and SystemVerilog
- Embedded C/C: Expertise in embedded software development and debugging
- Hardware Schematics and Datasheets: Proficient in understanding and interpreting hardware schematics and datasheets
- Software and Hardware Integration: Experienced in seamless integration of software and hardware
- Hardware Debugging: Skilled in diagnosing and resolving hardware-related issues
- FPGA Design and Automation: Proficient in using Python and Tcl for automation and testing, including Make for build automation
Accomplishments
Awarded Group Recognition for significant contributions to Fabric NoC Validation
Timeline
FPGA Silicon Validation Engineer
Intel Microelectronics (M) Sdn. Bhd
01.2022 - Current
Validation Engineer II
DSS Software Solutions Sdn Bhd
08.2020 - 12.2021
FPGA Design Engineer
Benchmark Electronics
04.2019 - 08.2020
Senior Engineer
Sigma Microsystems Pvt Ltd
01.2016 - 04.2019
Bachelor of Engineering - Electronics And Communications Engineering
VTU - Visvesvaraya Technological University
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