TEE SHENG YANG
Kajang
Summary
Dynamic Design Verification Engineer with a proven track record at Intel Malaysia, excelling in integrated circuit design and IP verification. Adept at utilizing UVM methodology and fostering collaboration to identify and resolve design issues early. Committed to delivering high-quality validation tests that enhance functionality and compliance.
Overview
7
7
years of professional experience
Work History
Design Verification Engineer
Intel Malaysia
Penang
07.2021 - Current
- Executed full-chip RTL integration and validation tests, ensuring compliance and functionality.
- Developed comprehensive test plans for integrated circuit design integrity verification.
- Collaborated with designers to identify bugs early in development using debugging techniques.
- Utilized UVM methodology to build components of the verification environment, such as drivers and monitors.
- Troubleshot integration issues, providing timely resolutions to maintain project timelines.
PROJECT ENGINEER ASSISTANT (INDUSTRIAL TRAINEE)
WILLOWGLEN
06.2019 - 09.2019
- Assisted in Electrified double-tracking railway project by (KTMB)
- In charge of Card Access System (CAS), Communication system.
- Provide necessary layout drawings and documents for each station.
- Design the cable color code for each components in the Card Access system controller.
- Do final checking and improvement on Detail Design Documents based on the feedback from the engineer manager and assistant manager.
SUMMER WORK AND TRAVEL PROGRAM
YMCA OF THE ROCKIES
Colorado
06.2018 - 09.2018
- Cultural exchange program.
- Responsible to keep all the hotel rooms, camping cabins, and eating place clean all the time.
- Responsible to prepare ingredients for dishes in the kitchen.
Education
Master in Engineering With Honours in Electrical And Electronic Engineering. -
THE UNIVERSITY OF NOTTINGHAM MALAYSIA CAMPUS
Semenyih, Selangor, Malaysia.07.2021
Foundation In Engineering. -
THE UNIVERSITY OF NOTTINGHAM MALAYSIA CAMPUS
Semenyih, Selangor, Malaysia.06.2017
Skills
- UVM methodology
- Integrated circuit design
- Collaboration skills
- IP verification
- SoC integration
- Design validation and debugging
Hobbies and Interests
- Travel
- Badminton
- Squash
- Swimming
- Board games
- Video games
Phone Numbers
(+60) 17-281 2745, (+60) 3-8741 0382
Languages
English
Advanced (C1)
C1
Chinese (Mandarin)
Native
Native
Malay
Intermediate (B1)
B1
Timeline
Design Verification Engineer
Intel Malaysia
07.2021 - Current
PROJECT ENGINEER ASSISTANT (INDUSTRIAL TRAINEE)
WILLOWGLEN
06.2019 - 09.2019
SUMMER WORK AND TRAVEL PROGRAM
YMCA OF THE ROCKIES
06.2018 - 09.2018
Master in Engineering With Honours in Electrical And Electronic Engineering. -
THE UNIVERSITY OF NOTTINGHAM MALAYSIA CAMPUS
Foundation In Engineering. -
THE UNIVERSITY OF NOTTINGHAM MALAYSIA CAMPUS
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