Tan Kean Lee
Staff Circuit Design Engineer
Summary
Engineering professional with thorough background in hardware
systems development and circuit design. Possesses strong drive for
achieving results and excels in collaborative environments.
Renowned for problem-solving abilities and adaptability to evolving
project needs, ensuring efficient and reliable circuit designs with
various skills.
Recognized for innovative minds with holder of 1 patents (Motorola
Solutions Inc.) and filed in 2019.
Detail-oriented individual with exceptional communication and
project management skills. Proven ability to handle multiple tasks
effectively and efficiently in fast-paced environments.
Overview
19
19
years of professional experience
Work History
Staff Circuit Design Engineer
Skyechip
01.2024 - Current
- Design and develop complex digital circuits of high speed memory interfaces using cutting-edge CMOS tech and EDA tools.
- Responsible for circuit design of Delay lines blocks and other subblocks include and not limited to output counter, feedback divider, lock detector, coarse delay line, fine delay line, phase interpolators, combiner, etc
- Start from floorplanning, performing simulations, and reliability verifications
- Work closely with layout designers (floor planning, SI improvement, EMIR issue etc.)
- Closing timing with Prime Time
Senior Analog Circuit Design Engineer
Intel Corporation
01.2022 - 01.2024
- Responsible for custom circuit design of LAB (Logic Array Block)
- Sub blocks include SRAM
- Develop test bench (text based HSPICE) to perform functional (READ, WRITE, etc) and reliability verifications
- Optimize the performance on PPA (Power, performance, area)
- Responsible to collaborate with architects, layout team, design automation team,etc in various tasks and problem solving
- Leading timing model characterization using Siliconsmart, timing closure with Primetime, reviewing STA with timing lead
Senior Electrical Engineer
Motorola Solutions Inc.
01.2010 - 01.2022
- Responsible for design and development of Motorola Audio Accessories such as RSM, earpiece, headsets, etc
- Experience in drawing schematic using Cadence
- Understand layout design
- Solid design experience in digital and logic circuitry, involving microcontroller, crystal clock, etc. with hands-on troubleshooting experience
- Familiar with electrical characterization/ timing analysis that involving communication protocol such as I2C, USB, UART
- Experience in audio/acoustic field
- Able to evaluate the potential risk and design test, able to debug and provide root cause analysis, and recommend solutions to fix or improve product reliability and field performance
- Experience with various test instruments including: Oscilloscope (to analyze the signal integrity, debugging, etc), spectrum analyzer (to measure the signal interference), bluetooth tester (for RF/Power/Modulation/BER Test), frequency counter (ppm measurement), audio equipments such as Communication analyzer, etc
- Experience in various product qualification and regulatory test including: -EMC Test (Radiated Immunity Test, Emission test, ESD test), Acoustic test (speaker loudness, microphone sensitivity, maximum audio safety test), Bluetooth Test, Battery Life Test (current drain measurement)
- Understand datasheet for electronic parts (microcontroller, microphone, speaker, diode, ferrite beads, etc)
- Understand Labview script
- Appointed as Microcontroller Section Lead, Flex
section (2019-2022). - Job and Responsibilities: Design and develop
microcontroller section, clock section and flexes,
Reviewed PCB layout, Paper assessed the series
of microcontroller at market and recommend
suitable one for product, Actively worked with SW
team on HSID (Hardware and Software Interface
Documentation) to design pin configuration/
assignment/mapping for microcontroller,
Evaluated the microcontroller either with
GreenPak simulation tools from vendor or using
EVK board with oscilloscope, Evaluated the
internal as well as the external reference crystal,
Studied on the external flash memory, Evaluated
the potential risk and carried out the test such as
USB, I2C, Crystal clock measurement, Prepared
and reviewed DFMEA - Appointed as PCN EE Lead -for Accessories
Department (2019-2021). - Job and Responsibilities: Managed the risk of
EOL/shortage component, including recommend
suitable replacement, generate test plan,
leading and coordinate the team of engineers
(layout engineers, material engineers, test
engineers, etc) to works on qualification,
compliance with all regulatory approvals and
product performance: Advice the PCN front liner
on the time and engineering effort required,
Worked with material engineers and supplier to
paper assess the part replacement, Assessed &
strategized the EE effort to meet the budgeted
timeline and resource, specifies minimum of
samples to obtain statistically valid data,
Proposed Hours and Cost estimation for
procurement team, Worked with business team
to ensure the impacted product continuity are
met in accordance with business strategy and
roadmap, and provide technical advice,
Communicate with suppliers on build samples,
factory test, build schedule, Reviewed test
report/factory buy off data/ qual data/ cpk data
from supplier or factory, Managed the
documents and updates in Agile such as product datasheet update, BOM, Provided guidance and
lead the team of professional engineers to
complete with productivity, Ensure the smooth
and timely execution until the PCN closed.
Have leadership, project and people
management, good communication and good
rapport across team, accountable. - Appointed (extended role) as Innovation Lead for
Accessories Department (2021). - Job and Responsibilities: Drive the innovation
culture and train new junior engineer to write
patent, Organized and led extensive
brainstorming workshop across department for
idea collaboration, Conducted personal sharing
on experience getting patent with all Accessory
EE engineers (2020), Familiar and experience with
prior art study, Able to recognize novelty and
patentability of one art or disclosure. - Have innovative mind and influencing among
peers. - Role: Technical • support Engineer.
- Job and Responsibilities:
Travelled to Mexico site as key person between
Mexico counterpart and Penang project team,
to coordinate the build and setup the factory
test, Provided onsite training and guidance,
reworked the sample and troubleshoot on spot
when issue happens, In Penang, as key person to
evaluate Bluetooth IC from CSR (acquired by
Qualcomm in 2015). Key engineer to evaluate
and qualify Bluetooth IC on product (BQTF). - Travelled to Schaumburg, US to transfer the
product knowledge from Schaumburg to Penang
before Schaumburg plant closed down,
Coordinated the transfer of the test equipment,
tools, products, etc. - Appointed as Project EE Lead.
- Job and Responsibilities: As program lead- To
offer the shipping accessories for different radios,
Actively coordinated with various stakeholders
(project/program manager, architect, regulatory
lab, business team, supplier, radio team) cross
functionally for all engineering activities and
qualification, Solved interference issue that
encountered across radio, by rootcause out the culprit and recommend optimum capacitor
value as solution, Supervised Proto, P1, P2,etc
builds at supplier site.
NPI Engineer
Inari (Penang) Sdn Bhd
01.2009 - 01.2010
- Involved in new product release, product failure/ lower yield investigation for RF IC.
Product Development Engineer
Spansion
01.2007 - 01.2009
- Involved in NOR Flash Memory characterization and evaluation.
Education
Electronic Degree - Engineering
USM Engineering
01.2007
Publications
- (Main author/contributor) Alter VP Response before VP responding to caller
- (Co-author/contributor) Dragging and Releasing a Field of a Form Triggers Camera and Analytics to Automatically Fill the Information
Additional info
- Initiative to learn and fast learner e.g. Learnt labview, android mobile apps (personal interest)
- Innovative. Passion and sensitive to new technology and invention
- Able to lead and manage people cross functionally with positive attitude to accomplish the goal within budgeted time without compromise the quality of product
- Discipline in delivering tasks on time
- Analytical experience in solving problems with data driven result
- Easier to adopt in various working environment
Patent
(Main author/contributor) System and method for talkburst initiator selection of talkgroup participants https://patents.google.com/patent/US20210051449A1
Additional Information
Patent filed: System and method for talkburst
initiator selection of talkgroup participants,
(https://patents.google.com/patent
/US20210051449A1),
Paper: Alter VP Response before VP responding to
caller,
Paper: Dragging and Releasing a Field of a Form
Triggers Camera and Analytics to Automatically Fill
the Information
Timeline
Staff Circuit Design Engineer
Skyechip
01.2024 - Current
Senior Analog Circuit Design Engineer
Intel Corporation
01.2022 - 01.2024
Senior Electrical Engineer
Motorola Solutions Inc.
01.2010 - 01.2022
NPI Engineer
Inari (Penang) Sdn Bhd
01.2009 - 01.2010
Product Development Engineer
Spansion
01.2007 - 01.2009
Electronic Degree - Engineering
USM Engineering
Similar Profiles
KISHAN PALKISHAN PAL
Analog Circuit Design Engineer at LeadIC Design PVT LTDAnalog Circuit Design Engineer at LeadIC Design PVT LTD
Ratnala Venkata PrasadRatnala Venkata Prasad
Analog Circuit Design Engineer at Incise Infotech LimitedAnalog Circuit Design Engineer at Incise Infotech Limited
Tzu-Ting YangTzu-Ting Yang
RF Circuit Design Engineer Intern at Compal ElectronicsRF Circuit Design Engineer Intern at Compal Electronics