Summary
Overview
Work History
Education
Skills
Timeline
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STEEVEN PHILLIPS ANTHONY

Bukit Mertajam, Penang

Summary

Dynamic Product Development Engineering Manager at Intel with a proven track record in driving innovations and optimizing debug methodologies. Skilled in project coordination and guiding professional development, I enhance lab throughput and reduce debug cycle time. Expertise in FIB tools and budget management ensures effective resource allocation and team success.

Overview

10
10
years of professional experience

Work History

Product Development Engineering Manager

Intel
04.2020 - Current
  • Manage day to day task by regularly engage in tool operations and contribute to debug strategy discussions.
  • Encourage development of new FIB techniques, debug methodologies, and process improvements to decrease the debug cycle time.
  • Define objectives for technology readiness, debug capability, and process roadmap alignment for future products.
  • Work closely with silicon design, product development, and platform teams to understand and planning of future debug support.
  • Ensure tool availability, optimize lab throughput, and plan for on demand cases such as PRQ, FACR, and MRB requests.
  • Sync FIB capabilities with fab process evolution with active trainings by Engineers before each product PO (Power On)
  • Develop a structured onboarding and skills development plan for new hires and cross-training across tools and techniques.
  • Set clear performance goals, conduct regular 1:1s, provide feedback, and recognize high performers.
  • Promote open communication and shared learning across global sites on daily activities by the team
  • Monitor circuit edit success rates, tool uptime, and FA for defect reduction initiatives.
  • Be the primary point of contact for debug support across internal customers.

Senior Component Debug Engineer

Intel
04.2015 - 04.2020
  • Perform physical microsurgery at transistor level (NMOS/PMOS) using Focused Ion Beam tool (FIB) for most of Intel's products ranging from Intel 4 to Intel 7 and TSMC's fabrication process such as TSMC 3nm, 5nm, 7nm using tools such as Centrios Advanced Circuit Edit System and Taipan G2+ Circuit Edit System. Connection and circuit modification are done at base layers and metal layers referring to the project's layout. Physical transistor level surgery is needed to validate test patterns, fuse unlocking, failure injection and waveform analysis before Product Release Qualification (PRQ), Failure Analysis Customer Return (FACR) and Material Review Board (MRB) units.
  • Provide solutions that have an impact within the discipline on multiple products for requester such as the CD, DE, PDE, SV et. new debug tools and debug methodology for new fab processes, which will be implemented across all labs to support all MPE lab products.
  • Owns driving solutions to meet future requirements in that area. Expected to drive innovations and breakthroughs to meet new product requirements or gaps in technology.
  • Develop new applications, characterizations and lab system.
  • Equipment owner for Thermo Scientific Centrios Advanced Circuit Edit System and Taipan G2+ Circuit Edit System. Ensure tools (Centrios, Taipan, Helios) are maintained, calibrated to minimize the tool down time. Manage its spares and consumables within its quarter budget.
  • Sound knowledge in Linux machine and CAD-NAV, responsible for maintaining, upgrading and ensuring fully functioning layout is in place prior to Silicon arrival.
  • Support readiness activities and provide support for all silicon debug requests. Responsible to provide silicon debug support on FIB circuit edit and sample prep MOB support.
  • New technology FIB process development/improvement, provide new products characterization, and training to all team members.
  • Perform cross-sections on units to understand the failures or FIB process defects at the transistor level using the Helios 5 PFIB UXe.
  • Publish debug case studies, and best practices for cross-site teams.

Education

Bachelor of Electrical And Electronics Engineering -

University Tenaga Nasional
Bangi, Selangor, Malaysia
09-2007

Skills

  • Project coordination
  • Goal-oriented planning
  • Guiding professional development
  • Budget coordination

Timeline

Product Development Engineering Manager

Intel
04.2020 - Current

Senior Component Debug Engineer

Intel
04.2015 - 04.2020

Bachelor of Electrical And Electronics Engineering -

University Tenaga Nasional

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STEEVEN PHILLIPS ANTHONY