Summary
Overview
Work History
Education
Skills
Software
Timeline
Generic
Saravanakumar Sivam

Saravanakumar Sivam

Test Process Engineer
Negeri Sembilan

Summary

Accomplished Engineer with a proven track record at ON Semiconductor and Jabil, enhancing process development and leading cross-functional teams to success. Expert in test verification and adept at project management, I significantly improved product yield and streamlined NPI projects. Renowned for adaptability and leadership, I excel in fast-paced environments, driving innovation and efficiency.

Overview

4
4
years of professional experience
3
3
Languages

Work History

Engineer II - Final Test & Process

ON Semiconductor
04.2024 - Current
  • Established and maintained positive working relationships with stakeholders to coordinate test engineering lot disposition activities, ensuring weekly KPI targets and yield improvement objectives were met.
  • Proficient in test engineering lot verification, including analyzing X-ray images to evaluate wire bonding and die quality using decapsulation imaging. Released lots following detailed test data log and distribution analysis.
  • Skilled in test data analysis using JMP and Exansio, with expertise in identifying anomalous test distributions and assessing potential risks.
  • Planned and executed engineering evaluations for new test programs, NPI, and on-hold lot risk assessments.
  • Acted as temporary lead in managing team operations and coordinating tasks during manager’s absence, ensuring smooth workflows and timely decision-making.
  • Collaborated with test development teams to qualify and document new test programs, debug issues, and implement solutions.
  • Coordinated with Product Engineers to manage wafer lot disposition, including low-yield lot risk assessments and analysis.
  • Experienced in engineering verification on tester platforms such as Eagle ETS88, ETS300, ETS364, Powertech QT4100, QT5120, and QT6000.
  • Proficient in test handler systems, including Ismeca NT16/NX16, SRM, Tesec MAP, Rasco, Multitest Tri-Temp, and Ueno Seiki.

Engineer I - Final Test & Process

ON Semiconductor
07.2022 - 04.2024
  • Conducted process failure analysis and investigations, delivering detailed reports for internal quality issues and customer complaints. Supported EFAR 8D investigations, ensuring D3 closure within a three-day cycle time.
  • Developed and updated FMEA, Control Plans, process flows, and Work Instructions, meeting stringent deadlines to support IATF audit compliance.
  • Reorganized and restructured the Final Test FMEA (400 rows), aligning it with AIAG and VDA standards for enhanced documentation clarity.
  • Led a paperless cost-saving project by migrating paper-based checklists to the SFC system for digital data collection.
  • Collaborated with cross-functional IT teams to implement automated system validation, improving detection accuracy for incorrect device markings

Product and Process Engineer

Jabil
05.2021 - 07.2022
  • Led PCBA assembly process and drive product yield improvement from Frontend to Backend Assembly and Final Inspection.
  • Led Assembly process for new product launch through scale-up activities from pilot-scale testing to full-scale production implementation.
  • Design and conducted DOE, reverse engineering and process commonality to analyse customer complaints, reduce process losses and improve process yield.
  • Collaborated with cross-functional teams to plan and execute NPI projects and resolve sustain product and process issue.
  • Developed and updated FMEA, Control Plan, Process Flow, Visual Aid and PCN documentation for NPI and sustaining products.
  • Coordinated with SQE to resolve raw material issues affecting product quality and functionality.
  • Coordinated with quality assurance to investigate and rectify customer complaints, support 8D closure and ensuring customer satisfaction.
  • Streamlined communication between R&D and production teams to facilitating smoother NPI.
  • Join forces and execute a containment strategy with the Equipment team in rectifying to machine breakdown issue and communicate with customer for temporary process deviation approval.

Education

Masters Degree In Engineering - Mechatronics And Automatic Control

Universiti Teknologi Malaysia
Johor
02.2021

Bachelor Of Mechanical Engineering -

Multimedia University
Malacca
06.2019

Skills

Process development

Software

Microsoft Excel

Microsoft Word

Microsoft Powerpoint

JMP - Data Analysis

Exansio - Data Analysis

PE Editor - Powertech

ETS Shell - Eagle Tester

Timeline

Engineer II - Final Test & Process

ON Semiconductor
04.2024 - Current

Engineer I - Final Test & Process

ON Semiconductor
07.2022 - 04.2024

Product and Process Engineer

Jabil
05.2021 - 07.2022

Masters Degree In Engineering - Mechatronics And Automatic Control

Universiti Teknologi Malaysia

Bachelor Of Mechanical Engineering -

Multimedia University
Saravanakumar SivamTest Process Engineer