Ranganath Sharma Khandavally
Bayan Lepas
Summary
Senior engineering professional with proven track record in leading complex projects and driving technical innovation. Known for strong expertise in software development, system architecture, and project management. Excellent collaborator, adaptable to changing demands, and consistently delivers results through effective team leadership and problem-solving skills. Skilled in optimizing processes, ensuring quality standards, and enhancing operational efficiency.
Overview
12
12
years of professional experience
1
1
Certification
Work History
SENIOR LEAD ENGINEER (Client: AMD Singapore)
UST Global Sdn Bhd.
06.2023 - 03.2025
- AMD Versal FPGA Post Silicon AMBA family protocols Pin Timing Validation in ATE.
- Compilation of base designs as required and generate the pdi file, dcp file. Create the loopback logic and simulate the loopback feature in design level.
- Identify the pins input and output pins and create a pin file to use as input for generating the bit streams of Input and Output pin timing and Generating bit streams for FuncHold (Tsh) and Setup (Tsu), Clock to output (Tck).
- Validate the base patterns using pdi and elf file in Bench.
- Generate the npi and cfi files using the dcp file of the base design and test the base patterns of npi and cfi on the AFX board.
- Generate the parallel groups of pattern A and Pattern B to further test the pin timing on ATE with multiple pins simultaneously.
- Creating the def and sub file scripts to submit the bitstreams to the ATE.
- Analyze the test results submitted to ATE and Debug and rerun the tests with failure analysis.
- Creating reports and sharing the reports with stakeholders.
SENIOR LEAD ENGINEER (Client: Intel Corporation.)
UST Global Sdn Bhd.
06.2023 - 03.2025
- Intel Agilex FPGA HPS IP validation, Memory Validation, Marginality Testing, Timing Characterization, Functional PVT validation.
- Validating the Clock Manager IP on LPDDR4, LPDDR5 MuDV boards to characterize the timing data with Memory IO to ensure the u-boot flow happening smoothly.
- Validating the Clock Manager IP on DDR5 MuCV board to characterize the timing data of with Memory IO to ensure the u-boot flow happening smoothly.
- Compiling the GHRD designs to test the ECC and Non ECC DIMM for HPS PVE validation.
- Intel Agilex FPGA Hard Processor System (HPS) IP and FPGA IP validation.
- Clock Manager, I2C and I3C IP bare metal functional test content development and porting and test validation.
- Capturing the timing characterization data and comparing it with the data sheet and presenting the data to CEG.
- RTL Design generation, development and compilation for the functional test features and generate the sof design files using Quartus Prime.
- IP Functional Validation including the PVT and timing PVT.
SENIOR LEAD ENGINEER (Client: Intel Corporation.)
UST Global Sdn Bhd.
11.2018 - 01.2023
- Zephyr RTOS Industrial Use Case Workload Application Development and Validation with ARM Cortex M7 Chipset.
- Test content enablement on CRB, RVP SoC Functional Validation, SST, Integration of third-party libraries such as lib light modbus with Zephyr RTOS stack for RS485 modbus relay functioning using RS232.
- SoC and Platform debugging followed by closure of customer issues and participating in cross functional team meetings and working closely with team to resolve the Platform, SoC issues
- Test content development of I2C, SPI BME280 sensors in Zephyr RTOS for Cortex M7 Chipset.
- Test content development of UART, QEP, PWM and CAN using Zephyr RTOS for Cortex M7.
- Test content development of TSN featured RGMII and SGMII Zephyr RTOS using modbus tcp.
- Test content development of all low speed and highspeed IP’s in Yocto for platform FV.
- Firmware loading and testing using core boot with secure signing and stitching.
- Firmware loading and performing the memtest in UEFI.
- Test content development to create the guest OS inside the Host OS using the virt-manager and analyze the performance of the virtualization with multiple Guest OS.
SENIOR LEAD ENGINEER (Client: Intel Corporation.)
UST Global Sdn Bhd.
05.2017 - 11.2018
- Mutiara Firmware Support Automation
- Fetch the core boot from archives and compiling the firmware and generating rom files and binary files using the build tools.
- Automate the process of loading the firmware using stitching and signing tools and program the firmware on the boards.
- Automate the UEFI test cases, flashing OS and validating the OS test cases in regression.
SENIOR ENGINEER (Client: Intel Corporation.)
UST Global Sdn Bhd.
12.2015 - 04.2017
- Functional Safety Memory Controller ECC and Non ECC DIMM test automation
- Firmware stitching and signing and programming the FW and perform the memtest in UEFI.
- Developing scripts in Python to inject error and error reporting develop the wrapper to execute the Python SV using Python interpreter.
- Automated the test scripts to perform test execution for caching agent, core, home agents.
- Testing the Memory Controller with Functional safety test cases and updating the test result in Excel sheet using Python. Perform the test using different third-party vendor memories such as Samsung, Micron, SK Hynix, Intel and validate.
- Test case creation electrical validation of memory controller on FuSa boards. Filing the HSD and test case reporting and debugging the issues.
SENIOR LEAD ENGINEER (Client: Intel Corporation.)
UST Global Sdn Bhd.
01.2015 - 11.2015
- Intel Server Management Tool
- Worked as Post Silicon Functional Validation on high end server variants chipsets and contributed for automation of Server Management Tool with Python Web Framework Flask.
- Worked with different SKU types to validate Xeon CPU.
- Worked with Intel de’ facto IPMI calls to monitor system health, system hardware, system environment, report the FRU’s, Log system events, recover systems, alert users, control chassis power remotely, read and set LAN configuration parameters, print sensor values.
- Collaborated with server configuration management tools like Nagios, Chef, and Puppet to remotely manage the remote servers in network.
SENIOR LEAD ENGINEER (Client: Intel Corporation.)
UST Global Sdn Bhd.
05.2014 - 12.2014
- Open Stack Orchestration with Small Cell
- Worked in setting up of the Edge cloud on Intel Rangeley platform and RCC-DFF. Setting up of the EPC, EVM and TFTP servers. Deploying the LTE stack on the EVM using TFTP server and configuring the third-party Polaris EPC. Involved in creating and setting up Amazon EC2 cloud tenants.
- Setting up the Open Stack Havana multi node cloud setup and transferring the iperf traffic, audio, and video packets through the Open stack cloud tenants passthrough the EPC to EVM to LTE- UE (5G user). Check the performance and loss of packets using L3 protocols using Wireshark packet analysis tool. Involved in writing the scripts to automate the edge cloud setup and its functionalities
SENIOR LEAD ENGINEER (Client: Intel Corporation.)
UST Global Sdn Bhd
08.2013 - 04.2014
- Enhanced Platform Architecture Quality Assessment (EPAQA)
- Worked in understanding the requirement specific document for Enhanced Platform Architecture for Quick Assist to design and implementation for EPAQA with no multi tenancy algorithm for Intel SRIOV supported with encryption and decryption capable hardware platform.
- Worked in implementing the database changes to nova module tables for no multi tenancy algorithm requirement and preparing the Unit test cases and integration testing.
- Worked in porting the devstack code to Open Stack to support the customizations of EPAQA software patch to support hardware product.
Education
MTech - Information Technology Networking
VIT University
Vellore, Tamilnadu05.2008
Skills
- Working experience with DDR4, DDR5, LPDDR4, LPDDR5 MuDV and MuCV boards for electrical validation to characterize the memory electrical characteristics
- Working experience in Functional Safety memory controller error injection, error detection and error correction using Python SV and collecting the data of memory controller using automation
- Working experience in the ECC and Non ECC DIMM test cases execution for DDR
- Working experience in BIOS, UEFI, Core boot functional validation including memtest
- Working experience in DDR Initialization, DDR Calibration and DDR repair test flow
- Working experience in multidisciplinary in the design creation, compilation, electrical validation and timing characterization, functional validation, and utilization of memory IO and mixed signal architectures
- Working experience using the different vendor DDR memory devices for the industry standard IO applications and custom Intel interfaces
- Working experience using different sets of GHRD to validate the functionality of LPDDR4 and LPDDR5 boards
- Intel Agilex Family FPGA IP validation of Clock Manager, I2C, I3C
- Create, modify and compile the RTL design using Quartus Prime Design Software for the HPS and FPGA
- Post-Silicon Validation, Timing, PVT and IP bring up in FPGA ARM SoC Agilex 5
- Completed the DFT course training from Chip Edge, Bangalore
- Test Plan Creation for Functional and Timing test coverage and automation solution bring up for Clock Manager IP functional, timing systems margin validation PVT
- System Debugging of Intel Core, Intel Atom, Intel Xeon Server and SoC platforms
- Worked on multiple SoC Power On activities and Engineering Board bring ups including RVP and CRB’s SUT bench setup, host setup and connecting the interposers seating the silicon clean up
- Good understanding of board level hardware schematics
- Having Good knowledge in RTOS application programming
- Experience in using lab equipment’s such as Oscilloscopes, Protocol analyzers/Exercisers, Clock Generators, Logic Analyzers, JTAG Based debuggers
- Worked with geographically diverse teams in issue debugging and execution ability to work in collaborative environment and lead
- Able analytical person, excellent analytical, troubleshooting, and Strong debugging skills
- Domain: Pre-silicon, Post silicon Validation, Automation, Python Web Application development, Open Stack Orchestration and API development
- Operating System: Linux, Windows, Android
- RTOS: Zephyr RTOS, VxWorks
- Programming: Python, Python SV, Flask, Django, C, C
- Circuit Validation: Tx Equalization, Rx Equalization, Duty Cycle, Period, Frequency
- Tools: Lauterbach Tool Chain, ARM Tool Chain, ITPII, JTAG, Lecroy USB Analyzer, Lecroy PCIe Analyzer, Logic Analyzers, Spirent Analyzers
- Simulation Environment: Simics setup from scratch, development of pre silicon test content and Validation
- Emulation Environment: Synopsis HFPGA Emulation Platform environment with Add On AIC
- Function Generators: Familiar with Agilent 81134A model
- Languages: English, Telugu, Hindi, Sanskrit, Basic Kannada and Tamil
- Cloud Systems: Open Stack, AmazonEC2, Sahara (Hadoop or Spark) on top of Open Stack api’s such as Nova, Keystone and Horizon
- Data engineering
- Manufacturing
- Network engineering
- Microservices architecture
- Requirements analysis
- API development
- Performance optimization
- Teamwork
- Teamwork and collaboration
- System design
- Software architecture
- Technical leadership
Certification
- Online DFT Course, ChipEdge Technologies - March 2023-June2023
Extracurricular Activity
Participated in Colors program part of CSR Penang, Malaysia SENIOR VOLUNTEER - FIRST AID Apr 2014 – PRESENT
Awards
PSDC Trained on Industry 4.0 IoT applications Penang, Malaysia. PRE - POST SILICON VALIDATION Nov. 2019, Received Best Performance award for Validation and SW Debug support., EHL Chip bring up PO Penang, Malaysia Oct 2019, Client appreciation and Performance awards for leading Platform Validation Regression platform bring ups and SW Debug support., GLK PRQ Support Appreciation Penang, Malaysia, I have received appreciation for GLK core SOC Peripheral’s bring up and debug support., Received recognition and appreciation awards from Client for EHL UCIS functional validation, content development and debug support, Completed the Chip Edge 4 months DFT Certification Course in Mar23-June23 completed the course project in ATPG.
Languages
English
Professional Working
Hindi
Limited Working
Telugu
Native or Bilingual
Timeline
SENIOR LEAD ENGINEER (Client: AMD Singapore)
UST Global Sdn Bhd.
06.2023 - 03.2025
SENIOR LEAD ENGINEER (Client: Intel Corporation.)
UST Global Sdn Bhd.
06.2023 - 03.2025
SENIOR LEAD ENGINEER (Client: Intel Corporation.)
UST Global Sdn Bhd.
11.2018 - 01.2023
SENIOR LEAD ENGINEER (Client: Intel Corporation.)
UST Global Sdn Bhd.
05.2017 - 11.2018
SENIOR ENGINEER (Client: Intel Corporation.)
UST Global Sdn Bhd.
12.2015 - 04.2017
SENIOR LEAD ENGINEER (Client: Intel Corporation.)
UST Global Sdn Bhd.
01.2015 - 11.2015
SENIOR LEAD ENGINEER (Client: Intel Corporation.)
UST Global Sdn Bhd.
05.2014 - 12.2014
SENIOR LEAD ENGINEER (Client: Intel Corporation.)
UST Global Sdn Bhd
08.2013 - 04.2014
MTech - Information Technology Networking
VIT University