Raghavendra Sharma
Analog Mixed Signal IP Architect
Bayan Lepas
Summary
Analytical and highly adaptable professional with over 20 years of success in leading engineering innovation, DDR5/LP5/LP6 PHY Circuit design and micro architecture, USB2 Circuit design and micro architecture And design of DLL's, IO circuits DC/DC converters for high-growth organizations. Repeated success in developing circuitry, solving technical problems, and overseeing processes. Broad knowledge and success in both product development, develop new architectures,requirements gathering/assessment, and full life cycle project management of analog/mixed signal designing concepts, practices, and processes. Skilled team leader and trainer with a track record of directing multiple tasks efficiently to ensure on target completion of deliverables.
Overview
21
21
years of professional experience
2012
2012
years of post-secondary education
Work History
DDR PHY: Circuit micro-Architect & Tech Lead
Intel technologies
11.2017 - Current
- Company Overview: Leading technology company specializing in semiconductor manufacturing and design
- Website: https://www.intel.com
- Derive Top down specification and design of LP6/DDR5/LP5/DDR4/LP4 circuits like TX/Power-gates/LDOs and miscellaneous circuits like elevated gnd rail generation circuit, DFX circuits like analog and digital view in FinFet trigate Based 10nm/7nm/3nm and Tyche based gate all around 18A Intel process for Intel 9th Gen , 10th Gen client products
- Derive Top down specification and design of DDR5/LP5/LP6 clocking circuits like TXDLL/RXDLL/PI/DCC/Serializer in FinFet trigate Based 10nm/7nm/3nm and Tyche based gate all around 18A Intel process for Intel 9th Gen , 10th Gen client products
- Generate Jitter table and Analyze noise contribution along DDR PHY Transmit and receive path
- Spec out Deterministic and Random jitter for each individual components of Clocking blocks to meet the JDEC spec
- Lead and drive Mix signal validation for analog circuits using Logic stimulus and feedback Designers for circuit margins
- Interact with DDR cross functional teams for DDR top level integration and validation
- Reliability and aging analysis of circuits and provide guidance to analog layout designers on matching, reducing noise coupling, floor planning and custom route of critical signals
- Developed junior staff through targeted coaching and mentoring, improving capabilities and competencies of technical teams
- Collaborated effectively with stakeholders, partners and project teams to aid timely delivery against technical roadmap.
Analog Design, PHY Circuit Architect
INTEL MICROELECTRONICS
12.2013 - 11.2017
- Design USB2 circuits for different platforms like servers, client application, IOTG and mobile
- Perform troubleshooting, investigate product failures, identify and implement solutions
- Manage several projects focused on operational excellence, pre and post silicon support
- Resolved and root caused silicon issues related to USB2 HS disconnect across many enterprise-wide Intel products platforms
- Facilitate numerous USB 2.0 physical layer transceiver (PHY) integrated circuit initiatives
- Serve as subject matter expert and key architecture on analog blocks including TX, RX, PLL, calibration circuits for USB2, and post Silicon debug activities
- Ensure that USB2 design across different platforms in mobile and server applications
- Oversee USB 2.0 physical layer Post Si Debug processes, USB2 protocols, and key debug Silicon issues
- Complemented for resolving many customer issues related to USB2 and received high level Intel Awards including divisional recognition award
- Designed SQ detector, disconnect detector, USB1.1 classic receiver, and USB2 receiver
Senior Design Engineer II
MANDATE CHIPS & CIRCUITS PVT LTD
08.2010 - 10.2013
- Served as senior design engineer and team lead for power analog department
- Managed team of engineers that was responsible for design of DCDC Buck regulator chip with 3 modes of operations
- Facilitated design of 2 channel WLED driver for 0.18um Dongbu technology
- Collaborated with other engineer on system level designs, block level specification and schematic design, top level design, top level integration, verification, layout floor planning, and post silicon validation of buck converter and WLED drivers
- Designed a Dickson charge pump for a load current of 250uA and an Output voltage of 35V
Senior Design Engineer
TESLA SEMICONDUCTOR PVT LTD & Future Techno Designs
11.2003 - 07.2010
- Company Overview: A semiconductor company involved in the design and development of analog and mixed signal ICs
- Developed and managed development and design of Analog and Mixed Signal ICs for semiconductor company
- Design of PLL's and IO and LVDS circuits for different product application
- Designed implemented PFD and charge pump circuits for different PLL designs for frequency synthesizers
- Modeling of PLL loop parameters like KVCO, loop filter RC values, charge pump currents
- Identified design process to satisfy client needs, minimize costs, and also limit potential operational challenges
- Executed layout and post layout simulation of LVDS transmitter
- Served as subject matter expert and provided support for LVDS RX design
- Designed LVDS Transmitter in 40nm TSMC for 288MHz input signal and 50ps of skew specification
- Led development and implementation of 40nm Clock generator design, precoding IO-2 – SFI4 TX/RX buffers
- Performed schematic and layout design of Clock Tree synthesis (CTS), post layout simulations
- Simulation of 3.2GHz SERDES, D-jitter PLL, and AREA EFFICIENT PLL projects
Education
Master of Science - Micro Electronics
MANIPAL UNIVERSITY
Bachelor of Engineering - Electronics & communication
BMS COLLEGE OF ENGINEERING
Skills
Software development lifecycle
Technical problem solving
Team collaboration
Requirements gathering
Performance optimization
Analytical thinking
Technical analysis
Stakeholder management
Team leadership
Client communication
Issue troubleshooting
Coaching and mentoring
Risk assessment
Debugging techniques
Solution architecture
Cross-functional collaboration
Accomplishments
- US patent, Back Power Protection circuit for Generic High Voltage tolerant IO, Intel, ATTORNEY-CLIENT PRIVILEGED COMMUNICATION. Disclosure#116532
- Selected Publication, MDMTC: Future Generation low power USB2 PHY Architecture Solution (eUSB2)
- DTTC 2019, Infinite Weaklock: A novel power saving feature for a capless supply controlled DLL in DDR5/LPDDR5 memory PHY
- DTTC 2021, Debug of weak lock issue during functional validation of DDR4 memory on RKL-S
- DTTC 2022
- DTTC 2024
Timeline
DDR PHY: Circuit micro-Architect & Tech Lead
Intel technologies
11.2017 - Current
Analog Design, PHY Circuit Architect
INTEL MICROELECTRONICS
12.2013 - 11.2017
Senior Design Engineer II
MANDATE CHIPS & CIRCUITS PVT LTD
08.2010 - 10.2013
Senior Design Engineer
TESLA SEMICONDUCTOR PVT LTD & Future Techno Designs
11.2003 - 07.2010
Bachelor of Engineering - Electronics & communication
BMS COLLEGE OF ENGINEERING
Master of Science - Micro Electronics
MANIPAL UNIVERSITY
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