Raghavendra Sharma

• Responsible for the schematic and layout design of Clock Tree synthesis (CTS), post layout simulations
• Facilitated 3.2GHz SERDES, D-jitter PLL, and AREA EFFICIENT PLL projects.

· Derive Top down specification and design of for DDR5/LP5/DDR4/LP4 circuits like TX/powergates/LDOs and misc circuits like elevated gnd rail generation circuit, DFX circuits like analog and digital view in FinFet trigate Based 10nm/7nm/3nm and Tyche based gate all around 18A Intel process for Intel 9th Gen , 10th Gen client products.

· Derive Top down specification and design of for DDR5/LP5 clocking circuits like TXDLL/RXDLL/PI/DCC/Serializer in FinFet trigate Based 10nm/7nm/3nm and Tyche based gate all around 18A Intel process for Intel 9th Gen , 10th Gen client products.

· Lead and drive Mix signal validation for analog circuits using Logic stimulus and feedback Designers for circuit margins. Interact with DDR cross functional teams for DDR top level integration and validation.

· collaborate with Signal integrity teams for memory interface modeling, simulation and characterization. DDR system jitter analysis of TX/RX and clocking paths.

· Reliability and aging analysis of DDR5/LP5 circuits and provide guidance to analog layout designers on matching, reducing noise coupling, flor planning and custom route of critical signals.

· Developed junior staff through targeted coaching and mentoring, improving capabilities and competencies of technical teams.

· Collaborated effectively with stakeholders, partners and project teams to aid timely delivery against technical roadmaps.

Broad knowledge and success in both product development, requirements gathering/assessment and full life cycle project management of analog/mixed signal designing concepts, practices, and processes

• Direct concurrent product development initiatives for a leading semiconductors and related device manufacturer
• Perform research, discuss requirements with stakeholders, create new concepts, conduct tests, and analyze project feasibility
• Collaborate with management, quality assurance, operations teams on technical concerns
• Design USB2 circuits for different platforms like servers, client application, IOTG and mobile
• Perform troubleshooting, investigate product failures, identify and implement solutions
• Key Accomplishments:
• Manage several projects focused on operational excellence, pre and post silicon support
• Resolved and root caused silicon issues related to USB2 HS disconnect across many enterprise-wide Intel products platforms
• Facilitate numerous USB 2.0 physical layer transceiver (PHY) integrated circuit initiatives
• Serve as a subject matter expert and key architecture on analog blocks including TX, RX, PLL, calibration circuits for USB2, and post Silicon debug activities
• Ensure that USB2 design across different platforms in mobile and server applications
• Oversee the USB 2.0 physical layer Post Si Debug processes, USB2 protocols, and key debug Silicon issues
• Complemented for resolving many customer issues related to USB2 and received high level Intel Awards including a divisional recognition award
• Designed SQ detector, disconnect detector, USB1.1 classic receiver, and USB2 receiver
• Conduct in-depth research and failure analysis on various USB2 related issues.

• Implemented product designs for a semiconductor product development company
• Served as a senior design engineer for the power analog department
• Managed a team of engineers that was responsible for the design of DCDC Buck regulator chip with 3 modes of operations
• Implemented strategies to resolve customer qualification, integration and testing issues
• Key Accomplishments:
• Implemented corrective actions and launched root cause investigations for tracking technical issues
• Facilitated the design of 2 channel WLED driver for 0.18um Dongbu technology
• Collaborated with other engineer on system level designs, block level specification and schematic design, top level design, top level integration, verification, layout floor planning, and post silicon validation of buck converter and WLED drivers
• Participated in several initiatives including; feasibility study on on-chip charge-pump for Tlense Driver
• Designed a Dickson charge pump for a load current of 250uA and an Output voltage of 35V.

• Developed and managed the development and design of Analog and Mixed Signal ICs for a semiconductor company
• Facilitated the design of PLL’s and IO and LVDS circuits for different product application
• Key Accomplishments:
• Designed implemented PFD and charge pump circuits for different PLL designs for frequency synthesizers
• Modeling of PLL loop parameters like KVCO, loop filter RC values, charge pump currents
• Identified design process to satisfy client needs, minimize costs, and also limit potential operational challenges
• Executed layout and post layout simulation of LVDS transmitter
• Served as a subject matter expert and provided support for the LVDS RX design
• Designed a LVDS Transmitter in 40nm TSMC for a 288MHz input signal and 50ps of skew specification
• Led the development and implementation of 40nm Clock generator design, precoding IO-2 – SFI4 TX/RX buffers.