Pritchard Primus
Bayan Lepas, Penang
Summary
IC Design Engineer seeking a position in which my experiences and training can help to increase the value of the organization.
Overview
5
5
years of professional experience
Work History
Senior Design Engineer
Oppstar Technology
Bayan Lepas, Penang
06.2022 - Current
- RTL to gate netlist synthesis, using Cadence Genus Synthesis. (16nm process node by TSMC) which includes general DFT implementation for scan coverage, power-gated/low power design implementation and developing timing constraints per design specification.
- Static timing analysis, using Cadence Tempus / Synopsys PrimeTime which covers timing and reliability analysis on post-layout database, in various modes and RC corners, developed and maintained timing constraints for functional and scan related modes and developed ECO script for post-layout timing, design rule violations and clock-tree modification to drive timing closure.
- Layout place & route, using Cadence Innovus which involves floor-planning, power mesh built, placement optimization, CTS, routing and DFM optimization, post-layout verification (LEC, DRC/LVS, power analysis) and implementing ECO for timing/reliability sign-off.
Advance Design Engineer
Oppstar Technology
Bayan Lepas, Penang
06.2020 - 06.2022
- Provides IC design and system solutions to MNCs and local SMEs.
Design Engineer
Oppstar Technology
Bayan Lepas, Penang
08.2017 - 06.2020
- Provides IC design and system solutions to MNCs and local SMEs.
Technical Assistant
Jabatan Penyiaran Malaysia (RTM)
Kota Kinabalu, Sabah
06.2016 - 09.2016
- Went for internship and involved in media library system project.
Education
Bachelor of Science - Electrical-Mechatronic Engineering
Universiti Teknologi Malaysia
Johor, Malaysia06.2017
Skills
- Good knowledge in physical design (RTL-to-gate netlist)
- Familiar with high speed digital and mixed signal IC design
- Good Knowledge in languages relevant to the ASIC development process including Verilog, TCL and Unix/Perl Scripting
- Good understanding in static timing analysis (STA)
- Skilled in time management
- Self-motivated, excellent communication skills and ability to excel in a team environment
- Excellent written and verbal communication
- Professional report writing
Languages
English
Proficient
C2
Malay
Proficient
C2
Timeline
Senior Design Engineer
Oppstar Technology
06.2022 - Current
Advance Design Engineer
Oppstar Technology
06.2020 - 06.2022
Design Engineer
Oppstar Technology
08.2017 - 06.2020
Technical Assistant
Jabatan Penyiaran Malaysia (RTM)
06.2016 - 09.2016
Bachelor of Science - Electrical-Mechatronic Engineering
Universiti Teknologi Malaysia