PREETHAM SHEENAPPA GOWDA TENKILA
Process Technology Design Engineer - Grade 8
Bayan Lepas, Penang
Summary
12+ Years of experience in the field Physical Design, working as Process Technology Design Engineer on lower technology nodes.
Overview
11
11
years of professional experience
Work History
Process Technology Design Engineer - Grade 8
Intel Microelectronics Sdn. Bhd.
02.2023 - Current
- Working as an individual contributor on arm Testchip with Intel18 process
- Worked as a PPAC design engineer on Intel4A, Intel 3 and Intel18 tech nodes.
- Analyzed and interpreted data to identify trends and recommend improvements.
Senior Physical Design Engineer
AMD from AdeptChips
6 2022 - 12.2022
- Working as a Team Lead for 6nm project
- Handled 105 partitions as a team lead along with a subordinate
- Project has critical timing/placement blocks
- Instance count of partitions range from 20K to 1.5million instances and 6nm technology
- Team Size 45 Members
Senior Physical Design Engineer
Qualcomm from Tsilicon
03.2022 - 05.2022
- Working as a Team Lead for 4nm project
- Handled 40 partitions as a team lead
- Project has critical timing/placement blocks
- Instance count of partitions range from 50K to 8Million instances and 4nm technology
- Team Size 20 Members
Senior Physical Design Engineer
INTEL from Infenecs
12.2020 - 01.2022
- Working as a Team Lead for DDG team for the MTL base die project
- Handled 12 partitions as a team lead
- Project has critical timing/placement blocks
- Instance count of partitions range from 50K to 1.5Million instances and 22nm technology
- Team Size 25 Members
Senior Physical Design Engineer
Juniper Networks from L&T
09.2020 - 11.2020
- Worked as an Individual Contributor for handling 3 timing critical blocks and 14 non-timing critical partitions
- Congestion critical partitions
- IR fixes were critical to consume
- Functional ECOs created a lot of timing violations
- Project Description 600K, 400K and 350K instances with 1.2GHz freq
- 7nm technology
- Team Size 14 Members
Senior Physical Design Engineer
AdeptChips from Tsilicon
08.2020 - 09.2020
- Worked as an Individual Contributor for DDRPHY block Placement fixes to handle the flop placement to reduce the overall block latency Timing closure
- Project Description 1.5 Million instances with 700MHz freq
- 28nm technology
- Team Size 12 Members
Senior Physical Design Engineer
INTEL from EXIMIUS
06.2019 - 06.2020
- Floorplan was critical as the block was macro dominant Clock tree implementation was tricky as some portion of the tree was built manually to ensure no crosstalk
- Worked on early clocking strategy to mitigate high clock skews
- 16nm DRCs were critical for closure
- Project Description 3 Million instances with 800MHz freq
- 16nm technology
- Team Size 5 Members
Senior Physical Design Engineer
Intel from Tessolve
09.2018 - 05.2019
- Subsystem level UPF fixes were critical to the closure Subsystem level pinning and floorplan were critical to placement Worked on clock skewing strategies to fixing timing issues
- Was a team member working on the big block to make sure all the Timing QoR is met
- Project Description 8million instances with 1.2GHz freq, 14nm technology
- Team Size 25 Members
Senior Physical Design Engineer
AMD from TSILICON
02.2018 - 07.2018
- Worked on the ICG cloning strategy for improved timing Worked on clock skewing strategies to fixing timing issues
- Leading a team of 3 and 4 blocks to make sure all the Timing QoR is met
- Working with the rest of the team, resolving their block issues and bringing their blocks to closure
- Project Description 1.2million instances, 1.2GHz frequency, 7nm technology
- Team Size 14 Members
Senior Physical Design Engineer
NXP from TSILICON
01.2017 - 12.2017
- Worked on synthesis using DCT and took the design for PNR Placement was critical as the logic distribution was critical and had to be controlled by bounds
- CTS was challenging as we had to meet a tight insertion delay targets Timing closure had involvement of lot of skewing techniques
- DRC closure was critical as we had to do few base changes to fix the DRCs
- Project Description 2.6million instances, 900MHz frequency, 16nm technology
- Team Size 20 Members
Senior Physical Design Engineer
INTEL from SANKALP
01.2015 - 11.2016
- Worked on flow automation on cadence/synopsys tools to bring up effective ways of PNR closure with minimal manual involvement Worked on different technology nodes ( 14nm and 10nm) and across different blocks Worked on PNR automation to get minimal QoR Project Description Worked on flow methodology for kit development on 14nm and 10nm
- Team Size 8 Members
Senior Physical Design Engineer
PMC from Sicon Design Technologies
06.2014 - 12.2014
- Worked on 3 blocks simultaneously and on Aprisa as the PNR tool Placement was critical as there were lot of congestion in the core and different strategies needed to fix them Timing closure on the 3 blocks DRC/LVS closure Project Description 350K, 400K and 600K instances with 750MHz freq
- 28nm technology
- Team Size 20 Members
Senior Physical Design Engineer
Qualcomm from Smartplay
04.2013 - 05.2014
- Placement timing was critical
- Had to try multiple experiments to resolve them
- Worked on CPF based designs, helped to team to resolve the CLP issues
- Timing closure DRC/LVS closure Project Description 1.3million, 800K 28nm and 600K 16nm technology
- Team Size 25 Members
Education
B.Tech Instrumentation Technology -
SJCE, Mysore
Skills
Good understandings of Physical design, timing closure and Physical verification
Have fair exposure to cadence EDA tools: Innovus
Have good exposure to Synopsys EDA tools: ICC, ICC2, Fusion Compiler
Basic understanding on synthesis flow
Have fair exposure to Tcl
Accomplishments
- HONOURS, AWARDS AND SCHOLARSHIPS
- 2nd place in the State Level Robotics competition at NITK, Surathkal
- 4th place in the National Level Robotics competition at SINE, IIT Bombay
- 2nd place in the Paper presentation competition on Robotics
Languages
kannada
Native language
English
Intermediate
B1
Hindi
Upper intermediate
B2
Telugu
Elementary
A2
Learning Python
Taking courses to learn python
Timeline
Process Technology Design Engineer - Grade 8
Intel Microelectronics Sdn. Bhd.
02.2023 - Current
Senior Physical Design Engineer
Qualcomm from Tsilicon
03.2022 - 05.2022
Senior Physical Design Engineer
INTEL from Infenecs
12.2020 - 01.2022
Senior Physical Design Engineer
Juniper Networks from L&T
09.2020 - 11.2020
Senior Physical Design Engineer
AdeptChips from Tsilicon
08.2020 - 09.2020
Senior Physical Design Engineer
INTEL from EXIMIUS
06.2019 - 06.2020
Senior Physical Design Engineer
Intel from Tessolve
09.2018 - 05.2019
Senior Physical Design Engineer
AMD from TSILICON
02.2018 - 07.2018
Senior Physical Design Engineer
NXP from TSILICON
01.2017 - 12.2017
Senior Physical Design Engineer
INTEL from SANKALP
01.2015 - 11.2016
Senior Physical Design Engineer
PMC from Sicon Design Technologies
06.2014 - 12.2014
Senior Physical Design Engineer
Qualcomm from Smartplay
04.2013 - 05.2014
Senior Physical Design Engineer
AMD from AdeptChips
6 2022 - 12.2022
B.Tech Instrumentation Technology -
SJCE, Mysore
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