Parthiban Parumjothee
Product Development Engineer
Bayan Lepas
Summary
Summary
13 years of experience in Semiconductor FA and Testing field, including test development and management in internal as well as multiple OSAT.
Over the year, experience in working on multiple class test platforms, developing and evaluating
multiple test contents for high volume run compatibility. On the personal side,I'm self motivated and very enthusiastic about new challenges in work and life.Result driven person and very adoptive to current dynamic changes.
Passionate about understanding how things works.
Overview
13
13
years of professional experience
4
4
Languages
Work History
PRODUCT DEVELOPMENT ENGINEER
Altera
10.2021 - Current
- Experienced in working on Altera Agilex7 product with 116Gb XCVR feature.
- Developed perl scripts to skip tool waiting time for efficiently manage pattern generations. This implementation piloted in selecting best FFE precursor and postcursor combination for Eyecheck test.
- Developed shmoo tools for identify the characterization of PAM4 and NRZ signal failures with IPO method. This results in rootcausing non effective CDR calibration in SERDES test development. This method further promoted to be automated to populate from raw ituff files.
- Increased overall product quality through meticulous test flow reviews and thorough testing procedures.
- Collaborated with other departments to facilitate successful project completion which includes setting up mUDV board bench for PRBS loopback tests using PhytonSV.
TEST DEVELOPMENT ENGINEER
Broadcom Inc
08.2016 - 10.2021
- Mixed signal devices, New product characterization, Test program releases, Yield improvement, TTR, post PRA device low yield debugs,
- Worked with designers for device characterization on Analog/Digital testing to improve better consistency in delivering test results from hardware and also software perspective. ADC,DAC tests, PRBS, SERDES, SCAN tests.
- Projects: Innovative approaches on pattern modification/ masking using Perl script to improve yield based on calculated risk from bench test results.
- Evaluate new hardware design, prototypes and proposals and recommend repair or design modifications, based on factors such test efficiency, CM accessibility.
- Contract manufacturing management: chair weekly meeting on delivering output, hardware related low yield causes, coaching on hardware debug, new BKM, process improvisation.
PRODUCT DEVELOPMENT ENGINEER
Intel Technology (M) Sdn Bhd
06.2013 - 08.2016
- Product transfer from NPI to High Volume Manufacturing. •
- Key Roles/Achievements.
- Key contributor in achieving IME Qualification granted for intel 1st 14nm SOC to be released for HVM mode in time to market.
- Collaborate with QnR for QA multiple temperatures socketing elimination prior to HVM. This effort saves redundant testing, saves tester capacity and reducing material flow Through put time. •
- Enabling selective smart inline retest to reduce invalid/marginal failure rate.
- 100% Elimination on reject validation prior to FA, based on data collection on minimum recovery rate bins. This high confident Improvement done liaising with Quality. •
- Enable datalog capturing for complicated mux pins testing's,contributes to faster fault isolations.
- Establishing standard RV procedure, BKM for junior engineers, Shmoo, 2nd cut debug procedure for HVM sustaining data Collection for continues test time reduction and test kill limit optimization.
- Chair Cold socket monitoring working group meetings to maintain healthy DPM.
FAILURE ANALYSIS ENGINEER
Intel Technology (M) Sdn Bhd
06.2011 - 06.2013
- Semiconductor/Wafer Fabrication - FAFI tools/ techniques Electrical- PLCCT, parametric analyzer, TDR, EOTPR, ImagingMicroscope, Image pro(soft), SEM, CSAM, Image overlay Mechanical- Destructive analysis, FIB, voltage contrast Chemical -EDA boiling, IMC etching, RIE Key Contribution - Actively participated in numerous hot issues/excursions in factory and providing decent finding to narrow down possible excursion modulators.
- Support on Q&R reliability Risk assessment to understand the impact on suspicious defect and drive the team in risk taking.
Education
Bachelor's Degree of Engineering - Microelectronics, Wafer fabrication & Semiconductor packaging
UNIVERSITY MALAYSIA PERLIS
Skills
UFLEX
my life philosophy
How you do anything is
how you do everything.
Timeline
PRODUCT DEVELOPMENT ENGINEER
Altera
10.2021 - Current
TEST DEVELOPMENT ENGINEER
Broadcom Inc
08.2016 - 10.2021
PRODUCT DEVELOPMENT ENGINEER
Intel Technology (M) Sdn Bhd
06.2013 - 08.2016
FAILURE ANALYSIS ENGINEER
Intel Technology (M) Sdn Bhd
06.2011 - 06.2013
Bachelor's Degree of Engineering - Microelectronics, Wafer fabrication & Semiconductor packaging
UNIVERSITY MALAYSIA PERLIS
Similar Profiles
Amit Lalchand WaghmareAmit Lalchand Waghmare
FPGA IP DESIGN ENGINEER at ALTERAFPGA IP DESIGN ENGINEER at ALTERA
Danny (Yuanli) DingDanny (Yuanli) Ding
FPGA IP Software Engineer (Grade 6) at AlteraFPGA IP Software Engineer (Grade 6) at Altera
Lisa RodriguezLisa Rodriguez
Business Operations Manager/Executive Assistant at AlteraBusiness Operations Manager/Executive Assistant at Altera
Marisol "ALEX" Reyes-VergaraMarisol "ALEX" Reyes-Vergara
SR Business Analyst Contractor at AlteraSR Business Analyst Contractor at Altera
Noor Maizura Binti Mohamad MohdNoor Maizura Binti Mohamad Mohd
Customer Service Cashier , Side Plant Supervisor at RJ Food CathererCustomer Service Cashier , Side Plant Supervisor at RJ Food Catherer