Enthusiastic engineer with close to 3 years of industrial experience across the semiconductor and manufacturing industry. Currently seeking a challenging career with a progressive tech company that provides an opportunity to capitalize on my technical skills in the electrical and electronic field.
Silicon design for Intel products and Intel Foundry customers
Key Responsibilities :
• Drives end-to-end development for silicon design from concept through tape-out & implements physical layout & routing of the silicon design.
• Works closely with cross-functional teams from silicon/packaging architects, semiconductor sort, die prep, metrology, fabrication and SI/PI engineers to meet their respective requirement & enabling NPI.
• Works through tight-timeline in an extremely fast-paced environment to meet the needs of customers.
• Managed multiple projects simultaneously while adhering to strict deadlines and maintaining a high level of attention to detail.
• Conducts design reviews, analyzes data, resolves design rules for design optimization & contributes to the maturity of the silicon process design kits (PDK).
• Streamlined the design process for increased efficiency by utilizing advanced CAD software tools.
• Led in producing and releasing sets of best-known-method documentation as references for fellow engineers, providing long-term values to the team
Awards:
Intel Q1'24 Assembly Test & Technology Development (ATTD) Division Recognition Award recipient - For completing the silicon design tape-out for foundry customer in an extremely tight timeline.
IC testchips package layout design for multi-project wafer program.
Key Responsibilities :
• Drives end-to-end development for package substrate design from concept through tape-out & implements
physical layout & routing of the package design.
• Performs package fit & routing studies to establish design, performance, & cost trade-offs.
• Works closely with silicon & hardware teams to optimize silicon-package-board performance & pinout
• Defines package design rules, conducts internal & external reviews, analyzes data, & resolves DRCs
to optimize package design.
• Completes documentation & collateral into the product lifecycle management system of record.
• Conducted stacking tests for 13 units of product pallets under various conditions to assess the stability and capability of newly proposed product packaging in meeting the conditions experienced at storage sites.
• Executing ANOVA Gauge Repeatability & Reproducibility (GR&R) studies on operators for 3 quality equipment (weigher, digital caliper, & jig plug gauge), successfully verified that the gauge measurement systems used are adequate for all applications
• Periodically analyzing the quantity & type of defects for internal & external returned products; prepared slides for the statistics of the returned products to be used for QA meeting
LINUX
Cadence Virtuoso
Siemens Mentor Xpedition Package Designer
Siemens Mentor Xpedition Substrate Integrator
Cadence PowerDC
Signal & Power Integrity
Stakeholder Management & Engagement
JMP
Presentation Skills