Financial markets
Hi, I’m
Karan Vashisth
Design and Verification Engineer
BAYAN LEPAS,PENANG
Summary
Self motivated and qualified Verification Engineer with good experience simulation as well formal technology. My attention to detail, problem-solving skills, and dedication to continuous improvement enable me to effectively validate complex designs and mitigate risks, ultimately ensuring the successful deployment of cutting-edge technologies in today's rapidly evolving semiconductor industry.
Overview
8
years of professional experience
Work History
Intel Microelectronics
Sr. Pre Silicon Verification Engineer
01.2022 - Current
Job overview
- Handling IP's like I2C , I3C , Security IP like Key Vault etc at Subsystem level as well as IP level.
- Develop verification plans on Subsystem Level as well as IP level.
- Hardware + Software co-verification , create tests based on C as well as System Verilog + UVM tests.
- Documents test plans and drives technical reviews of plans with design and architecture teams
- Strong technical leadership with good communication, interpersonal and problem-solving skills
- Replicates, root causes, and debugs issues in the pre-silicon environment.
Cadence Design Systems
Formal Verification Engineer
05.2018 - 12.2021
Job overview
- Worked on JasperGold tool apps like Coverage app , UNR app , FPV (formal property validation) , SuperLint app
- Validation of newly integrated features in tools. This involved creating unit level tests in SV and run it in formal environment.
- Involved in verification of Linting rules which were integrated in Superlint app.
- Established strong working relationships with clients through exceptional communication skills, fostering trust and collaboration.
- Resolved critical issues and ensured seamless integration at customer end.
NXP Semiconductors On Behalf Of Incise Infotech
SoC Verification Engineer
01.2016 - 05.2018
Job overview
- Create subsystem level testplan for IP's like I2C , Watchdog timer , DMA , timers etc.
- Executes verification plans and defines and runs system simulation to verify the design and uncover bugs.
- Testcases were created in C and SV + UVM language.
- Perform root causes analysis and debug issues in the Pre-silicon environment.
- Drive techinical review of testplans with Design and Architecture teams
Education
Uttar Pradesh Technical UniversityGhaziabad, India
Bachelor in Technology from Electronics And Communications Engineering
04.2001
Skills
Continuous integration tools
Hardware description language Verilog , VHDL , System Verilog , UVM
Protocol Knowledge like I2C , I3C , DMA , Watchdog , timers , Security IP Key Vault , AXI , AHB , architectures ,
Formal verification apps like Formal property verification app , Superlint app , UNR app , Coverage app , Assertion Based Verification
Familiar with Simulation tools like Xcelium (Cadence), Verdi (Synopsys) , Vmanager
Constraint Random Verification
Software-hardware co-verification
RTL design understanding
SystemVerilog expertise
SoC verification
UVM methodology
Digital circuit knowledge
Testbench development
Coverage (static functional)
Assertion-based verification
ASIC and FPGA design flow
Code coverage analysis
Verification planning
Interests
Social Media
Timeline
Sr. Pre Silicon Verification Engineer
Intel Microelectronics
01.2022 - Current
Formal Verification Engineer
Cadence Design Systems
05.2018 - 12.2021
SoC Verification Engineer
NXP Semiconductors On Behalf Of Incise Infotech
01.2016 - 05.2018
Uttar Pradesh Technical University
Bachelor in Technology from Electronics And Communications Engineering
04.2001