Kalpak Burgul

Working development of performance models and characterizing latency-bandwidth profiles for SoC interfaces on Intel Xeon servers.

Current exploration includes CXL memory performance profiling and identifying gaps with respect to core, cache coherency interconnects and DRAM-CXL memory balance.

• Worked on constructing SoC debug methodology for Intel GPU Max series 1100 code named Pontevecchio to meet performance goals based on Architectural targets.
• Charted mostly performance measurement procedures, profiling - performance debug flows, identifying gaps and causes for drop in performance and mitigation strategies with hardware and software workarounds to minimize perf drop.
• Delivered with this methodologies across multiple SoC interfaces
• Xe-link - multi GPU interface using SERDES for high bandwidth connectivity - Scaling from 2 to 8 GPU connectivity models. Worked on performance tuning for best bandwidth to provide inputs to software stack alignment with hardware config
• Intra-die connectivity - tile-to-tile interface to achieve better scaling across memory and compute per GPU
• GPU peer-to-peer connectivity using PCIE switch to scale across multi-GPU node
• PCIE interface - exploiting causes for gap and performance tuning to meet architectural targets.
• Implemented Multi-GPU-to-socket interface PCIE performance measurements exploiting blade level memory limitations across Xeon servers and performance impact with UPI for socket to socket interface
• Worked on memory performance tuning for HBM 2.0 chasing architectural targets to improve GPU local memory performance using various memory latency and timings parameters
• Worked on performance tuning debug of HPC and ML workloads which includes micro architecture level compute rate measurements and hardware performance debug to root cause SW and HW bugs and propose optimizations to improve performance across workloads

• Developed test cases for component verification in firmware at physical layer of LTE protocol stack and collaborated in debug for Modem simulation bring up.
• Developed test cases for functional checkout and debugging in Silicon Polaris Modem at component level

• Supported in functional validation during power-on at unit level debug for modem firmware with 3GPP standards
• Supported in configuration of base station simulator and 3G and 4G signal strength measurements