JOSEPH VICTOR SOOSAI PRAKASAM
Melaka
Summary
Accomplished Senior Process Engineer with a proven track record at Infineon Technologies, driving innovation and achieving significant cost savings. Expert in new product development and risk analysis, I excel in optimizing processes and fostering collaboration. My leadership led to a 35% increase in production efficiency and the filing of multiple patents.
Overview
24
24
years of professional experience
Work History
Senior Staff Engineer
Infineon Technologies SDN BHD Melaka
01.2016 - Current
Infineon technologies
Melaka
01.2016 - Current
Manager Engineering
SPEL SEMICONDUCTOR Ltd
11.2008 - 01.2016
- Semiconductor Assembly and Testing Career Development
Process Engineer
STATS CHIPPAC Ltd Singapore
07.2008 - 11.2008
- Semiconductor Assembly and Testing Family
Senior Process Engineer
SPEL SEMICONDUCTOR Ltd
07.2001 - 07.2008
- Employee of the year – 2014” at Natronics semiconductor
- For saving 35,k euros, for converting a wafer sorter machine to process, singulated QFN package [ 1 x 0.6 x 0.4 mm, micro UDFN]
- Awarded SSGB at Infineon for 31k Euro savings through yield improvement
- Increased production from 35 million to 50 million parts by systemizing production and round the clock monitoring
- Successfully Established QFN line setup [From DA to Pick and Place] in 2006, a major achievement in my career
- Responsible for new equipment benchmark, optimization, capability roadmaps and tooling equipment
- New product development, safe launch and mass production ramp up
- Good knowledge of FMEA, DOE, SPC, risk analysis
- Knowledge of die attach materials (conductive, insulated glue/paste), lead frame properties, die bond, flip chip and wafer technology and/or equipment troubleshooting will be an added advantage
- Drive value through innovation – 4 patents filed,2 under feasibility
- Able to generate new ideas, solutions even with limited time and complex situations
- Initiates and pushes ideas to implementation
- Ambitious and manage risks – key enabler in establishing Tiber module streamlined process flow
- Contributor in generating SMT characterization plan (PBHB lite for SMT processes)
- Consistent demonstration of results
- Systematic approach on process optimization and problem solving
- Key contributor in establishing Tiber module streamlined process flow 4A to fulfil quality, manufacturability and cost requirements
- Key contributor in the release and qualification of Tiber module supporting PSS PCS’ new Power Stage Modules, best-in-class leading solution for thermal performance and power efficiency
- Instrumental in starting up the DCDC module line in IFMY which supported various fast prototype builds including vertical module assembly is an efficient way which fueled the commercialization of Compact Module packages
- Derived a novel cost effective method to prevent solder remelting which became a building block in establishing process flow for Modules
- Key role in identification of interaction mechanism of solder ball issue with Denali bonding and solder printing
- Proposed design of stencil segmentation to compensate effect of Denali protrusion and SiPlace bond head limitation (contact bonding)
- Key role in identification of effective scrap removal method at singulation for Tiber to eliminate the copper burr accumulation under Denali Chip (850 k USD savings)
- Handled process development projects for Flip chip with less than 3 months timeline to meet T2M, Semiconductor Assembly and Testing Career Development
Principal Engineer
Infineon Technologies AG
11.2007
- IFX / OTCQX: IFNNY) is a leading semiconductor OEM company and has been included in the Sustainability Yearbook by the Swiss investment company RobecoSAM for the fifth consecutive time
- In the industry ranking, as well, Infineon holds one of the top positions
- Professional Experience and Profiles handled - Detailed, AIS unit Process development segment – FLIP CHIP, TSXP,ATSLP – Diffusion bonding and Flux dipping, SOLDER PRINTING, ,Vertical Module assembly line Successfully completed 21 process development projects for die-bond flip chip process and solder printing, Flux/solder Jetting for Module packages
- Developing new process controls and establishing robust recipe for new products
- Feasibility study and risk assessments on new products
- Study the behavior of solders at different temperature with different lead frame material
- Project Initiation, Planning, Managing, Change management, Execution, Monitoring and Closure
- Exposure to Global Change Management / Deviation & Decision Management
- FMEA / SPC and DOE of new product prior to release to production
- Statistical analysis of parameter behavior with JMP
- Leading task force and focus team to solve critical process issues and propose cost effective solutions
- Recording and Documentation of all process evaluations with theoretical, practical and statistical evidences for future references
- Analyze and ensure manufacturability of the new devices prior to Production release
- Handling Tosok/Texus- flip chip die bonder, ASM8312FC flip chip bonder , DEK Galaxy solder printing, Datacon 2200 Evo, Asymptek Nordson Forte
- Played a Prominent role in defining cost effective process flow for new module packages
- Filed 6 Patents under innovation platform
- Key Roles and Responsibilities
- Responsible for creating optimized process flow for module packages with innovative skills
- Responsible for process development of die bond attach processes (glue, flip chip diffusion bonding and flip chip flux dipping process)
- Establish and setup new diebond assembly process capabilities and materials including hands-on equipment setup
- Design and development of solder printing for Flip chip/ other semiconductor modules
- Innovate new process / Material essential for better product performance
- Monitor performance, quality and reliability of assembly processes
- Identify problems or unfavorable deviations and recommend and implement corrective and improvement actions through DOE
- Responsible for new equipment benchmark, optimization, capability roadmaps and tooling equipment
- Support new package development, ramp ups and platform extensions
- Support process roadmap updates for newly developed package technology
- Documentation review/approval of best practices and procedure in the process he/she is responsible for
- (process spec, work instructions, OCAP, failure catalogue, TWI, OJTI,FMEA.) Promotes sharing of technical knowledge and best practices within the group
- Facilitates discussions of unit process technical issues, supports team members in problem-solving methods/approach, and provides/consolidates recommendations to business process models related to unit process development (ex: One click PDR)
- Organizes schedule of regular FOL knowledge sharing sessions for the defined unit process during development meetings
- Consolidates the weekly high and low lights report of the unit process group Training programs and Visit abroad
- Have been to SINGAPORE for DISCO SAW SINGULATION BUY OFF, April 2006
- Visited KOREA for HANMI PICK AND PLACE TRAINING AND BUY OFF, April 2006
- Visited SINGAPORE FOR DISCO advanced maintenance training, June 2007
- Visited MALAYSIA [KEDAH]for Alphasem buy-off, Visited DYNACRAFT MALAYSIA [PENANG] to gain knowledge of QFN lead frame design and to sort out current issues related to DCI lead frames Nov ’07
- Visited HONGKONG IN SEPTEMBER 2010 for ASM DIE AD838 BUYOFF
- Visited TAIWAN IN DECEMBER 2010 for ALphasem buyoff
- Visited SINGAPORE IN 2011 APRIL for KNS ICON Buyoff and Training
- Visited Bangkok, Thailand in August 2015 for smart card module project.
Education
Bachelor’s Degree – B.E - Mechanical Engineering
Thiagarajar College of Engineering, Madurai Kamarajar University
Madurai04.2001
D.O.B -
01.1980
SIGMA GREEN BELT - Infineon -
Skills
- AND COMPETENCIES
- NEW PRODUCT DEVELOPMENT: [ NPD] – Responsibility added after 2012
- QFN / Leaded LEAD FRAME DESIGN [ Interacting with lead frame developers Dynacraft, QPL]
- Build sheet preparation, POD submission for customer approval
- Daily interaction with customers to understand their needs
- RISK ANALYSIS/ASSESMENT FOR NEW PRODUCT LAUNCH
- DESIGN FEASIBILITY AND PROCESSING FEASIBILITY FOR THE NEW PRODUCT
- Assisting customers in designing and selecting best suited raw materials for their products
- Preparing Budget or capital investment needed in every section to kick start a project
- Technical Interaction with machine vendors before releasing PO
- Technical interaction with internal team, to prepare them for smooth product launch
- DEFINING PROCESS FLOW AND OTHER DOCUMENT REVISION AND ALERT NEEDED
- BEFORE PRODUCT LAUNCH
- Periodical review with customers, vendors and passing on the necessary info to subordinates
- Risk assessment and process optimization for flip chip related solder printing process
- General roles
- Process improvement activities like, SPC monitoring, defining parameters for new process, initiating DOE
- Risk analysis for new products, procedure, PM and process related documentation for new products
- Defining control plans, revising documents and procedures for various processes
- OCAP, FMEA, Monthly cost saving and process improvement reports
- ISO documents control, release and revision
- Operators’ monthly training, new machine training and monitoring
- Training operators to meet the quality standards
- Data analysis to identify key process and production improvement areas
- Machine set-up and troubleshooting process related issues
- Monthly report submission, conducting weekly process improvement meeting
- Achievements
- Die bonder
- Defined and standardized the process parameters in new project LMP (QFN)
- Revised and fixed the Nozzle Collet and Plunge-up-pin standards
- DOE done on DIECRACK THROUGH post mount cure analysis, tape adhesiveness analysis and wafer surface roughness analysis
- DOE in Heel crack analysis for WB and freezed the parameter windows for the second bond
- Have been leading in cost cutting measures and saved up to 1500 USD per month, through innovative thinking
- Modified Alphasem 8032 to handle DAM and Fill COB of 40 x40 mm size
- Risk of poor wetting / improved Placement accuracy with ULGA frames analyzed for NSMD and SMD designs
- ULGA with SMD pads of 80um and 90um analyzed Recommended to go forward with 95-105 um SMD pad size to avoid chip tilting due to offset placement
- Analyzed the mechanism behind the chip tilting with MIS /LGA substrates and implemented key design features to improve placement accuracy
- Established the die bond process for thinner chip ( 25um Silicon 40um mold tape) for conventional package supporting RFS ( Thinnest available chip in the market is ~ 60um silicon)
- Currently handling Flip chip products with diffusion/Flux dip platform Along with flip chip attach through solder printing
- Proficient with hands-on experience on various assembly machines (i) Diebond/Flip chip: Texus, ASM, Datacon (ii) Chip/Clip and Lid attach: Datacon, ASM
- GAN Chip BLT calculation based on bump size developed and verified through actual build
- Solder Printing
- Derived and generated SMT characterization plan (PBHB lite) as a preliminary basis in characterizing module products
- Derived laminate design rules to have sufficient drain system around to minimize the solder voids, together with optimizing the solder printed volume
- Derived a novel cost effective method to prevent solder remelting which became a building block in establishing process flow for Modules
- Mentor for DS UPE and UPD colleagues for troubleshooting, data analysis, problem solving specific to SMT (screen print, component attach), dispensing, flip chip processes and AOI
- Excel tool creation to calculate solder volume wet / Dry BLT and automatic design rule verifications
- Dicing Saw – Package Singulation QFN (LMP)
- Played a prominent role in LMP lead frame designing
- DOE done to avoid copper dust at QFN singulation stage
- Implementation of Error free full automated SAW SINGULATION process with maximum UPH through time study
- Implemented cost effective improved blade life with best quality
- Cost reduction through increased productivity and sourced best singulation tape at reduced cost
- Played a prominent role in redefining the HALH ETCH design to eliminate the copper smear, and lead short after singulation
- Redesigned lead frame to reduce vertical and horizontal burr
- Dicing Saw –Wafer
- Reduced the Dicing DPM by standardizing the blades and optimizing process parameters
- DOE done on DIECRACK and preventive action taken to avoid it
- Pick and Place HANMI 2500
- Defined and standardized the machine and vision parameters in new project LMP (QFN) PACKAGE SIZE 3 x 3 and above
- Machine Exposure
- Back Grinding DFG 841
- Wafer saw Process and Maintenance - 2 YEARS
- DISCO DAD651, DFD651, DFD6360, DFD6340
- DEK SCREEN PRINTER - 10 years
- PLASMA CLEANING - ULTRA CLEAN PROCESS – 150 - 3 Years
- Die attach Process and Maintenance - 10 YEARS
- ALPHASEM 8002, 8032, ASM AD838,828,8312 FC
- SAW SINGULATION Process - 4 YEARS
- DFD 6360, DFD 6340, ADT MEGADICE 7200
- PICK AND PLACE Process - 4 YEARS
- HANMI PICK AND PLACE 2500
- TEXUS DBD4600 - 6 YEARS
- DATACON 2200 - 3 Years
- Asymptek forte - 1 Year
- Personal
- Ethical, reliable, collaborative, innovative and determined
- Able to work within multiple levels of management in a global company
- Ability to build relationships with employees, suppliers and customers
- Marital Status :
- Married
- Spouse Name : A Sudha Rani
- Nationality : Indian
Languages
Languages
Timeline
Senior Staff Engineer
Infineon Technologies SDN BHD Melaka
01.2016 - Current
Infineon technologies
01.2016 - Current
Manager Engineering
SPEL SEMICONDUCTOR Ltd
11.2008 - 01.2016
Process Engineer
STATS CHIPPAC Ltd Singapore
07.2008 - 11.2008
Principal Engineer
Infineon Technologies AG
11.2007
Senior Process Engineer
SPEL SEMICONDUCTOR Ltd
07.2001 - 07.2008
Bachelor’s Degree – B.E - Mechanical Engineering
Thiagarajar College of Engineering, Madurai Kamarajar University
D.O.B -
SIGMA GREEN BELT - Infineon -
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