JAGADISHWAR SADASHIVA

Spearheaded a dynamic consultancy firm, expertly leading and orchestrating a high-performance team, taking charge of Cerberus Machine Learning tool integration across various sectors.
Tackled intricate design issues, enhancing Power, Performance, and Area (PPA) metrics while adhering to Design Rule Compliance (DRC).
Boosted tool efficiency and runtime by optimizing synthesis and Place-and-Route (PNR) processes, along with issue resolution.
Partnered with block partition owners to overcome design obstacles and ensure on-schedule project completion.
Developed and improved synthesis and physical design methodologies, specializing in resolving low power design complications.
Facilitated effective teamwork with sub-partition leads to conquer design challenges and guarantee smooth project execution.
Achieved design compactness by focusing on area reduction and solving placement congestion issues.
Innovated clock routing techniques to reduce skew and latency, ensuring a stable clock distribution network.
Advanced pre-placement and pre-routing strategies for clocks and data nets to boost Quality of Results (QoR).
Implemented strategic placement guides early in the design to prevent routing congestion.
Adjusted sequential repeater placements to enhance IO interface timing paths.
Engineered scripting solutions for sequential flop pipelines, improving placement and timing performance.
Resolved a broad array of design violations, including DRC, LVS, antenna, max transition, and capacitance issues.
Integrated isolation and level shifter cells to effectively manage multi-voltage domain violations.
Addressed IR drop and electromigration (EM) concerns to ensure device longevity.
Preserved design integrity after iterations, minimizing the impact of functional ECOs on routing, DRC, and LVS.
Engaged with synthesis and RTL design specialists to refine project results and solve PnR complications.
Introduced innovative placement guides to reduce congestion in uniquely shaped partitions.
Significantly enhanced timing and minimized area problems in adjacent partitions with optimized floor planning.
Corrected timing discrepancies by strategically relocating Integrated Clock Gating (ICG) elements.
Maintained high-quality standards by resolving a wide range of violations, including base and metal density, DRC, LVS, and IR-EM.