Summary
Overview
Work History
Education
Skills
Accomplishments
Publications
Timeline
Generic

Fawaz Jumaah

Senior Embedded Systems Engineer
Sungai Ara, Bayan Lepas, Penang,Malaysia

Summary

Collaborative senior embedded systems engineer with embedded systems expertise and exceptional background coordinating with software, hardware and firmware engineers. Demonstrated excellence when connecting diverse contributors with varied talents to harmonize embedded systems to meet business goals and performance needs. Polished professional at creating well-aligned, cooperative workgroups.

Overview

7
7
years of post-secondary education
8
8
years of professional experience

Work History

Deep-Learning Software Validation Engineer

Intel Corporation
Bayan Lepas, Penang
05.2020 - Current
  • Validate, OpenVINO software and conjunction with PSG FPGA accelerators and ensure that OpenVINO works well with FPGAs.
  • Run neural network tests, measure OpenVINO quality and performance, and file issues to R&D team to address.
  • Work with R&D teams to help diagnose problems and ensure high quality of product.
  • Maintain internal validation infrastructure including development kits and servers.
  • Participate in projects to develop new products and algorithms.
  • Participate in system design and commissioning phase, interfacing directly with clients to ascertain clear, concise milestones for integration into development timelines.
  • Successfully achieved 6 applications porting from Deep-Learning Accelerator runtime environment to newer platforms to enhance business values.

Senior Embedded System and Applications Engineer

Intel Corporation
Bayan Lepas, Penang
07.2015 - 05.2020
  • Work in collaboration with existing teams located world-wide and responsible for delivery of reactive and proactive technical support in products to Intel customers, sales teams and design partners as necessary.
  • This may include delivery of formal training, how-to videos, and reference designs.
  • Communicating with Intel's customers mainly by web interface, e-mail and telephone.
  • Investigate support requests assigned and resolve these issues directly through appropriate use of simulation and other analysis tools, or by working with appropriate components and evaluation boards.
  • Lead Intel PSG reference design world wide core team, which is responsible for providing customers and online design store up to date reference designs for Intel PSG FPGA products.
  • Participate in development projects, possibly as part of international, cross organizational team and may include generation of collateral and reference designs.
  • Successfully achieved 12 projects with impact on customer's experience utilising Intel FPGAs

Embedded Systems Engineer

Innoventors
Penang, Malaysia, Malaysia
07.2012 - 02.2015
  • Collaborated with software, firmware and hardware engineers to develop complete embedded solutions.
  • Debugged software at rudimentary signal level, employing Eclipse to analyze performance and diagnose faults.
  • Modified existing code to replace problematic functions with optimized content.
  • Engineered software components for microcontrollers and sensors.
  • Designed Linux Kernel Application Programming Interfaces (APIs) for use in third-party software development.
  • Successfully achieved 4 successful projects per customers requirements.

Education

Ph.D. - Artificial Intelligence

College Of Artificial Intelligence, UPSI
Tanjong Malim, Perak, Malaysia
09.2017 - 12.2020

Master of Science - Computer and Embedded Systems Engineering

Universiti Putra Malaysia
Selangor, Malaysia
02.2012 - 10.2015

Skills

    FPGA Design Flow

undefined

Accomplishments

  • Linux-Based 10G ethernet application to control 10G MAC. This design was implemented on Zynq7000 SoC board from Xilinx.
  • Embedded system design of dynamic ranging camera application. This design utilised Cyclone V SoC development kit from Intel. The design captures data from ranging camera, process it, and send it as packet to DDR3 memory of linux-based system for post-processing.
  • Porting Intel OpenVINO C++ based applications. This project includes modifications of the existing OpenVINO applications from the legacy runtime platform to newer platforms.
  • MYO EMG Sensor reader on FPGA design implemented to collect EMG data using MYO ARM EMG sensor. The design involved Nios II processor, ADC controller, DMA, memory, Parallel IO IP, Flex sensor, and UART.
  • FPGA Diagnostic Reference Design aimed to test and validate the available IP's and peripherals on Cyclone V GX FPGA from intel. The design included, Nios II processor, CFI flash, LED, Push buttons, UART, switches and DMA.
  • Hand Gesture Detection on FPGA via Machine Learning. This design was a platform of a simple machine-learning based on static threshold detection algorithm running on FPGA and controlled via Nios II processor. The design included an accelerometer sensors, 8-channels ADC controller, and SDRAM.
  • Board Update Portal Design on FPGA. This application involves reading the bitstream of FPGA from ethernet cable and store it on Flash. The design was built on Arria 10 GX development kit.
  • I2C IP embedded driver. The development of an I2C IP embedded software driver. This driver was integrated with Nios II HAL and was validated by utilizing the APIs and accessing the defined registers.
  • UART TX/RX Design Validation on FPGA. This design was developed to validate the UART IP functionality. It included two UART IPs on each FPGA board. Each board has a processor to send/receive data via UART.
  • Cache Controller Memory Design. A cache memory controller was implemented. The project was achieved through two phases, the Digital design phase and the design simulation phase.
  • PrimeTime Web-Based Report Analyzer Tool. A project was used to analyze the Static Timing report from Synopsys PrimeTime and give the detailed information of the related design on webpages. This project had been implemented using PERL as the user side and PHP with MySql as the server side.

Publications

  • Jumaah, F. M., et al. "Technique for order performance by similarity to ideal
    solution for solving complex situations in multi-criteria optimization of the
    tracking channels of GPS baseband telecommunication receivers."
    Telecommunication Systems 68.3 (2018): 425-443.
  • Jumaah, F. M., et al. "Decision-making solution based multi-measurement design
    parameter for optimization of GPS receiver tracking channels in static and
    dynamic real-time positioning multipath environment." Measurement 118 (2018):
    83-95.
  • Jumaah, F. M., Hashim, S. J., Sidek, R. M., & Rokhani, F. Z. (2013, December).
    Low power GPS baseband receiver design. In 2013 4th Annual International
    Conference on Energy Aware Computing Systems and Applications (ICEAC) (pp.
    65-68). IEEE.
    Jumaah, F. M., Baskara, S., Sidek, R. M., & Rokhani, F. Z. (2015, August).
    PrimeTime web-based report analyzer (PTWRA) tool. In 2015 6th Asia
    Symposium on Quality Electronic Design (ASQED) (pp. 203-208). IEEE.
  • Zaidan, Aws Alaa, Bilal Bahaa Zaidan, M. Y. Qahtan, O. S. Albahri, A. S. Albahri,
    Mussab Alaa, Fawaz Mohammed Jumaah et al. "A survey on communication
    components for IoT-based technologies in smart homes." Telecommunication
    Systems 69, no. 1 (2018): 1-25.
  • Talal, M., Ramli, K. N., Zaidan, A. A., Zaidan, B. B., & Jumaa, F. (2020). Review
    on car-following sensor based and data-generation mapping for safety and traffic
    management and road map toward ITS. Vehicular Communications, 100280.

Timeline

Deep-Learning Software Validation Engineer

Intel Corporation
05.2020 - Current

Ph.D. - Artificial Intelligence

College Of Artificial Intelligence, UPSI
09.2017 - 12.2020

Senior Embedded System and Applications Engineer

Intel Corporation
07.2015 - 05.2020

Embedded Systems Engineer

Innoventors
07.2012 - 02.2015

Master of Science - Computer and Embedded Systems Engineering

Universiti Putra Malaysia
02.2012 - 10.2015
Fawaz JumaahSenior Embedded Systems Engineer