Synopsys ZeBu Server
Eapen Abraham A.
SoC Design Verification Engineer - Emulation
Bayan Lepas
Summary
Experienced design validation engineer with over 20 years of industry expertise, specializing in FPGA and emulation technologies. Recognized for excellence in these areas, brings a solid background in FPGA design and validation, along with a keen eye for detail when utilizing FPGA tools, emulation, and validation techniques. Demonstrates the ability to lead cross-functional teams in the design, development, and implementation of complex projects.
Overview
28
28
years of professional experience
6
6
years of post-secondary education
1
1
Certification
Work History
SoC Design Verification Engineer
Intel Microelectronics (DDG Group)
12.2020 - Current
- Leading Compute Die VATT Team developing Emulation models for Compute Cores.
- Validation of latest Intel SoC-CPU compute die (CDie)
- Emulation model builds and releases using Synopsys ZeBu Emulation platform
- Working on Synopsys ZeBu Server3/4/5 platforms.
- PoC for ZeBu model builds, issues and debug in DDG Malaysia group
Trained new engineers in FPGA and Emulation Flows.
Quartus Validation Engineer
Intel Microelectronics (PSG Group)
06.2019 - 12.2020
- Validated Partial Reconfiguration flows for Quartus and Stratix 10 FPGAs
- Owned PR Flow validation designs and test content.
- Created design for validation of FPGA Anti-tamper protection feature.
- Worked on enabling validation infrastructure for Intel OneApi.
- Design creation for validating Intel Quartus Design Suite
- Quartus Flows Validation for custom flows
- Flow validation, regression setup, bug tracking and closure
- Ensure tool flows meet set quality standards and are free of issues before final release.
Architect – Product Development / Project Manager
UST Global Malaysia Sdn Bhd
07.2016 - 04.2019
- Managing RTL Design, FPGA & Analog projects for UST Malaysia
- Team & Technical Management
- Requirement Analysis, Technical Feasibility analysis & Resource management
- Stakeholder engagement & management
- Project planning, scheduling & monitoring.
Freelancer
Self Employed
04.2014 - 06.2016
- Dealing in Financial Markets, Stock & Share Trading
- Looking to start-up Small-scale industry in the EMS (Electronic Manufacturing Services) sector
- Trained AAI staff in use of programmable logic (FPGA/CPLD) for their Radar systems.
Architect-Product Design (Consultant to Intel Mobile)
Harmon (Formerly Symphony Teleca Corp)
04.2013 - 04.2014
- Reported to the Program Manager and leading a team of resources, deputed to Intel Mobile Communications for FPGA Emulation
- Managed the team for the Hardware development activities, FPGA based design and FPGA Emulation
- Responsible for all phases of solution customization cycle, from business process study to UAT as well as for SDLC
- Involved in review and approval of the Design, Coding, Development Releases and Documentations etc, to ensure quality of deliverables
- Providing Technical and Functional guidance for solution implementation to client in multiple industry sectors
- Performing team administration as well as team development and people management initiatives for improvement of team productivity.
Lead Engineer MTS-III
Atria Logic Inc.
12.2012 - 04.2013
- Reported to CEO and led a team of 17 resources for management of the India Design Centre engaged in projects for design, verification and FPGA bring-up
- Built a team of Hardware and Software engineers working on the latest products
- Responsible for the bring up of Verification Infrastructure
- Involved in client interactions for project reviews and final delivery
- Involved in system architecture and RTL design.
Lead Engineer
MCCI Interconnect
03.2011 - 12.2012
- Reported to the Project Manager and supervised 3 resources in projects for design, verification and FPGA bring-up with the responsibilities of setting up verification environment for the same purpose as well as system architecture and RTL design.
Verification Engineer
Verification Partner Inc
05.2010 - 03.2011
- Responsible for Verification of ASICs & FPGAs using Verilog, SystemVerilog & SystemC
- Created Testplans, testbenches and verification architecture for Diamond FPGA project
- Worked on Verification of NAND Flash controller.
Assistant Professor - Electronics Department
Hindustan University
06.2009 - 05.2010
- Faculty in-Charge for PG VLSI & Embedded streams
- Taught Digital Design, VHDL, Verilog, Analog VLSI Design for M.Tech VLSI Stream
- Taught Microcontrollers & Embedded Design, RTOS for Embedded Streams
- Staff in charge for Final Year Projects for B.Tech ECE students.
Verification Engineer
Teradyne India Engineering
10.2008 - 04.2009
- Verification of Teradyne FPGA & ASICs using Verilog, SystemVerilog & SystemC
- Successfully verified Peidmont FPGA for Teradyne Ultra-Flex systems
- Led team in verification of TCIJ project
- Reported to Site Manager for Design & verification activities.
Senior Design Engineer
Cornet Technologies Pvt Ltd
01.2007 - 09.2008
- Design & Verification of Altera Cyclone based products and solutions
- Responsible for FPGA Digital design using VHDL & Verilog
- Led a team of 3 engineers in digital design and development
- Responsible for FPGA related board design, debugging and testing.
Design Engineer
Cornet Technology Pvt Ltd
03.2002 - 05.2004
- FPGA Design and verification using Xilinx Tools
- Design for custom data acquisition cards for defense sector.
Software Engineer
Brigade Solutions Pvt Ltd
01.1998 - 01.2001
- Worked on embedded software using Windows CE and Visual Studio MFC
- Worked on System software development using C/C++, Linux
- Design and testing of 8051 based embedded solutions for end customers
- Supporting end customers in resolving technical issues related to Embedded products.
Education
Master of Science - Advanced Micro-electronics & VLSI Design
International Institute of Information Technology
Pune 04.2004 - 04.2006
Bachelor of Engineering - Electronics & Communications Engineering
Sathyabama Engineering College, University of Madras
Chennai 01.1993 - 04.1997
Skills
ZeBu Emulation
FPGA design & Verification
FPGA Architecture (Intel & Xilinx)
FPGA Software/Hardware Validation
Verilog/VHDL
SystemVerilog
FPGA Tools (Intel/Xilinx)
Simulation Tools
Emulation Tools
Scripting - Perl, Tcl/Tk, Python
Accreditations
- Workshop on VLSI Design & Testing, IEEE & VLSI Society of India
- Telecom technologies - EWSD Switching exchanges, planning, Operation, installation & Maintenance
Certification
PRINCE2 Project Management
Software
Xilinx ISE/Vivado
Quartus Software Suite
ModelSim/QuestaSim
Cadence NC/Synopsys VCS
Timeline
SoC Design Verification Engineer
Intel Microelectronics (DDG Group)
12.2020 - Current
Quartus Validation Engineer
Intel Microelectronics (PSG Group)
06.2019 - 12.2020
Architect – Product Development / Project Manager
UST Global Malaysia Sdn Bhd
07.2016 - 04.2019
PRINCE2 Project Management
07-2014
Freelancer
Self Employed
04.2014 - 06.2016
Architect-Product Design (Consultant to Intel Mobile)
Harmon (Formerly Symphony Teleca Corp)
04.2013 - 04.2014
Lead Engineer MTS-III
Atria Logic Inc.
12.2012 - 04.2013
Lead Engineer
MCCI Interconnect
03.2011 - 12.2012
Verification Engineer
Verification Partner Inc
05.2010 - 03.2011
Assistant Professor - Electronics Department
Hindustan University
06.2009 - 05.2010
Verification Engineer
Teradyne India Engineering
10.2008 - 04.2009
Senior Design Engineer
Cornet Technologies Pvt Ltd
01.2007 - 09.2008
Master of Science - Advanced Micro-electronics & VLSI Design
International Institute of Information Technology
04.2004 - 04.2006
Design Engineer
Cornet Technology Pvt Ltd
03.2002 - 05.2004
Software Engineer
Brigade Solutions Pvt Ltd
01.1998 - 01.2001
Bachelor of Engineering - Electronics & Communications Engineering
Sathyabama Engineering College, University of Madras
01.1993 - 04.1997