Arun Pradhap Jeyaraj
Design Verification Engineer
Penang, Malaysia 10470
Summary
Senior Verification Engineer and Technical Leader with 18+ years of experience in ASIC/FPGA design verification across USB, RISC‑V, and Ethernet/TSN subsystems. Skilled in UVM/SystemVerilog methodologies, testbench development, and assertion‑based verification. Adept at debugging with industry‑standard simulators and driving coverage closure. Recognized for building high‑performance teams, mentoring engineers, and delivering reliable results in dynamic project environments. Backed by leadership certifications (Credly, Coursera, Six Sigma) and actively pursuing Lead roles in global semiconductor organizations.
Overview
19
19
years of professional experience
6
6
Certifications
Work History
FPGA Silicon Design Verification Engineer
Intel (Altera)
01.2024 - Current
- Leading TSN XGMAC verification with UVM & C test benches; achieved 100% functional coverage and ensured TSN compliance.
- Directed USB & GPIO verification in HPS subsystem, resolving 30+ critical protocol issues and accelerating project milestones by 15%.
- Designed verification test plans, debugged protocol issues, and coordinated with cross-site teams.
Senior ASIC Digital Design Engineer / Senior R&D Engineer
Synopsys India
01.2011 - 01.2022
- Development of USB2.0/3.0 VIPs; verified USB3.1 Device Controller IP.
- Built UVM environments, implemented compliance test suites, and debugged RTL.
- Mentored junior engineers, improving regression efficiency and reducing bug turnaround time.
Design Engineer
NSYS Design Systems
01.2010 - 01.2011
- Developed HSIC PHY, ULPI PHY models, and runtime configurable endpoint setup.
- Supported customer DUT integration and verification, ensuring smooth deployment.
Design Engineer
Vinchip Systems
01.2007 - 01.2010
- Developed USB2.0 test plans and tracked project metrics for successful delivery.
Education
B.E. - Electronics & Communications Engineering
Anna University
Tamil Nadu01-2007
Skills
Verification Methodologies: UVM, OVM, VMM; Assertion‑based verification
Languages & Standards: SystemVerilog (advanced expertise), functional coverage implementation
Testbench Development: UVM testbench architecture, reusable components, regression strategies
Debug & Simulation Tools: ModelSim, NCVerilog, VCS simulators
Planning & Strategy: Verification planning, coverage closure, metrics tracking
Certification
Leadership Development Experience – Credly
Timeline
FPGA Silicon Design Verification Engineer
Intel (Altera)
01.2024 - Current
Senior ASIC Digital Design Engineer / Senior R&D Engineer
Synopsys India
01.2011 - 01.2022
Design Engineer
NSYS Design Systems
01.2010 - 01.2011
Design Engineer
Vinchip Systems
01.2007 - 01.2010
B.E. - Electronics & Communications Engineering
Anna University